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PDF TC94A23F Data sheet ( Hoja de datos )
| Número de pieza | TC94A23F | |
| Descripción | Single-chip CD Processor with Built-in Controller | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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Toshiba CMOS Digital Integrated Circuit Silicon Monolithic
TC94A23F
Single-chip CD Processor with Built-in Controller
TC94A23F
TC94A23F is a single-chip CD processor for digital servo. It
incorporates a 4-bit microcontroller.
The controller features an LCD/LED driver, 4-channel 6-bit AD
converter, 2/3-line serial interface, buzzer, interrupt function, and
8-bit timer/counter. The CPU can select one of three crystal
oscillator operating clocks (16.9344 MHz, 4.5 MHz, and 75 kHz),
facilitating interface with the CD processor.
The CD processor incorporates sync separation protection and
interpolation, EFM decoder, error correction, digital equalizer for
servo, and servo controller. The CD processor also incorporates a
1-bit DA converter. In combination with RF amp TA2153FN or
TA2109F, TC94A23F can very simply configure an
adjustment-free CD player.
Weight: 1.6 g (typ.)
Thus, the IC is suitable for CD systems for automobiles and radio-cassette players.
Features
· Single-chip CD processor with built-in CMOS LCE/LED driver and 4-bit microcontroller
· Operating voltage:
At CD on: VDD = 4.5 to 5.5 V (typ. 5.0 V)
At CD off: VDD = 3.0 to 5.5 V (only CPU on)
· Current dissipation:
At CD on: IDD = 50 mA (typ.)
At CD off: IDD = 2 mA (with 4.5 MHz crystal oscillator, only CPU on)
At CD off: IDD = 0.3 mA (with 75 kHz crystal oscillator, only CPU on)
· Operating temperature range: Ta = -40~85°C
· Package:
QFP100-P-1420-0.65A (0.65-mm pitch, 2.7-mm thick)
· One-time PROM version:
TC94AP09F
1 2002-02-06
1 page  
Pin Function
TC94A23F
Pin
Number
Symbol
Pin Name
Function and Operation
Common signal output pins for the LCD panel.
97 COM1/OT1
Those pins configure matrix with S1 to S18
and display up to 72 segments.
The LCD can be driven by the 1/2 or 1/3 bias
98 COM2/OT2
method. When the 1/2 bias method is set,
three levels, MVDD, 1/2MVDD, and GND, are
output at 2-ms intervals at a 62.5 Hz cycle.
When the 1/3 bias method is set, four levels,
MVDD
MVDD, 1/3MVDD, 2/3MVDD, and GND, are
LCD common output output at 1-ms intervals at a 125 Hz cycle
/output port
(when either the 4.5 MHz or 75 kHz crystal
oscillator is used).
99 COM3/OT3
After system reset or clock stop execution is
released, the non-selected waveform (bias
voltage) is output. The DISP OFF bit is set to
0 and the common signal is output.
100 COM4/OT4
These pins can be switched to an output port
(Note 1) or LED driver pins by program. They
are usually used for digit output to drive the
LEDs.
Remarks
MVDD
Bias
voltage
5 2002-02-06
5 Page 
Pin
Number
69
70
71
72
73
Symbol
RFGC
TEBC
FMO
DMO
2VREF
Pin Name
Function and Operation
Control signal output pin for adjusting RF
amplitude.
Outputs three-level PWM signal
(PWM carrier = 88.2 kHz).
Tracking balance control signal output pin.
Outputs three-level PWM signal
(PWM carrier = 88.2 kHz).
Focus equalizer output pin.
Outputs three-level PWM signal
(PWM carrier = 88.2 kHz).
Disc equalizer output pin.
CD processor control
input/output
Outputs three-level PWM signal
(PWM carrier = 88.2 kHz for DSP block).
Analog reference voltage power supply pin
(2 ´ VREF)
74 SEL
APC circuit on/off signal output pin.
At laser on, high impedance at UHS = High; H
level output at UHS = High.
TC94A23F
Remarks
P2VREF
Rout3
VREF
¾
VDD
77 XVSS
80 XVDD
Power supply pins for CD crystal oscillator.
To control the CD processor power supply
and the controller power supply individually,
connect the MVDD and MVSS pins to the
power supply lines used by the VDD and VSS
pins.
¾
CD crystal oscillator input/output pins.
Connect a 16.9344 MHz crystal oscillator. The
clock is used as the CD system clock and
controller system clock.
78 XI
After system reset, this clock is supplied as
CD processor crystal the controller system clock and starts the
Rout1
oscillator pins CPU.
XO
The crystal oscillator can be halted by
program. If the 4.5 MHz or 75 kHz oscillator is
RfXT1
selected as the controller system clock, the
oscillator is halted by program when the CD
XVDD
processor is off.
79 XO
During execution of the CKSTP instruction,
oscillation halts.
(Note)
When switching the controller
system clock from the controller
oscillator to the CD crystal oscillator,
make sure that the CD crystal
oscillator is in stable state.
XI
XVSS
11 2002-02-06
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet TC94A23F.PDF ] | |
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