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PDF ICS501A Data sheet ( Hoja de datos )

Número de pieza ICS501A
Descripción LOCO PLL Clock Multiplier
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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ICS501A
LOCO™ PLL CLOCK MULTIPLIER
Description
The ICS501A LOCOTM is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 200
MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
Features
Packaged as 8-pin SOIC or die
ICS’ lowest cost PLL clock
Zero ppm multiplication error
Input crystal frequency of upto 27 MHz
Input clock frequency of upto 50 MHz
Output clock frequencies up to 200 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Nine selectable frequencies
Operating voltage of 3.3V
Tri-state output for board level testing
25mA drive capability at TTL levels
Ideal for oscillator replacement
Optimized for output frequencies of upto to 200 MHz
Industrial temperature version available
Advanced, low power CMOS process
Block Diagram
S1:0 2
Crystal or
Clock input
X1/ICLK
X2
Crystal
O s c illa to r
Optional crystal capacitors
VDD
PLL Clock
M u ltip lie r
Circuitry
and ROM
GND
OE
CLK
MDS 501A B
1
Revision 120704
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

1 page




ICS501A pdf
ICS501A
LOCO™ PLL Clock Multiplier
Parameter
Symbol Conditions
On-Chip Pull-up Resistor
Pin 7
Input Capacitance, S1, S0, and OE
Pins 4, 6, 7
Nominal Output Impedance
Min.
Typ.
270
4
20
Max.
Units
k
pF
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol Conditions
Min. Typ.
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 3.0 to 3.6V
FIN
FIN
FOUT
see page 2
see page 2
0°C to +70°C
-40°C to +85°C
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
PLL Bandwidth
tOR 0.8 to 2.0 V, Note 1
tOF 2.0 to 8.0 V, Note 1
tOD 1.5 V, up to 160
MHz
1
1
45 49-51
120
Output Enable Time, OE high to
output on
50
Output Disable Time, OE low to
tri-state
50
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
tja Deviation from mean
tjs
+70
25
Note 1: Measured with 15 pF load.
Max.
27
50
200
TBD
55
Units
MHz
MHz
MHz
MHz
ns
ns
%
kHz
ns
ns
ps
ps
MDS 501A B
5
Revision 120704
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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