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PDF ICM7224 Data sheet ( Hoja de datos )
| Número de pieza | ICM7224 | |
| Descripción | 41/2 Digit LCD Display Counter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICM7224 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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May 2001
®
NO RECOOBMSOMLEENTDEEPDRROEDPULCATCEMENT
ICM7224
41/2 Digit LCD Display Counter
Features
• High Frequency Counting - Guaranteed 15MHz, Typically
25MHz at 5V
• Low Power Operation - Typically Less Than 100µW
Quiescent
• STORE and RESET Inputs Permit Operation as
Frequency or Period Counter
• True COUNT INHIBIT Disables First Counter Stage
• CARRY Output for Cascading Four-Digit Blocks
• Schmitt-Trigger on the COUNT Input Allows Operation
in Noisy Environments or with Slowly Changing Inputs
• Leading Zero Blanking INput and OUTput for Correct
Leading Zero Blanking with Cascaded Devices
• Provides Complete Onboard Oscillator and Divider
Chain to Generate Backplane Frequency, or
Backplane Driver May be Disabled Allowing Segments
to be Slaved to a Master Backplane Signal
Pinout
ICM7224
(PDIP)
TOP VIEW
Description
The ICM7224 device is a high-performance, CMOS 41/2
digit counter, including decoder, output latch, display driver,
count inhibit, leading zero blanking, and reset circuitry.
The counter section provides direct static counting, guaran-
teed from DC to 15MHz, using a 5V ±10% supply over the
operating temperature range. At normal ambient tempera-
tures, the devices will typically count up to 25MHz. The
COUNT input is provided with a Schmitt trigger to allow
operation in noisy environments and correct counting with
slowly changing inputs. The COUNT INHIBIT, STORE and
RESET inputs allow a direct interface with the ICM7207 and
ICM7207A to implement a low cost, low power frequency
counter with a minimum component count.
These devices also incorporate several features intended to
simplify cascading four-digit blocks. The CARRY output
allows the counter to be cascaded, while the Leading Zero
Blanking INput and OUTput allows correct Leading Zero
Blanking between four-decade blocks. The BackPlane driver
of the LCD devices may be disabled, allowing the segments
to be slaved to another backplane signal, necessary when
using an eight or twelve digit, single backplane display.
These devices provide maximum count of 19999. The
display drivers are not of the multiplexed type and each dis-
play segment has its own individual drive pin, providing high
quality display outputs.
VDD
E1
G1
F1
BP
A2
B2
C2
D2
E2
G2
F2
A3
B3
C3
D3
E3
G3
F3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 D1
39 C1
38 B1
37 A1
36 OSCILLATOR
35 VSS
34 STORE
33 RESET
32 COUNT
31 COUNT INHIBIT
30 LZB OUT
29 LZB IN
28 CARRY
27 1/2 - DIGIT
26 F4
25 G4
24 E4
23 D4
22 C4
21 B4
Part Number Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
ICM7224IPL
-25 to 85 40 Ld PDIP
PKG.
NO.
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number 3168.2
1 page  
ICM7224
Control Input Definitions
In Table 1, VDD and VSS are considered to be normal oper-
ating input logic levels. Actual input low and high levels are
specified in the Operating Characteristics. For lowest power
consumption, input signals should swing over the full supply.
Detailed Description
The ICM7224 provides outputs suitable for driving conven-
tional 41/2 digit by seven segment LCD displays. It includes
29 individual segment drivers, a backplane driver, and a self-
contained oscillator and divider chain to generate the back-
plane frequency (See Functional Block Diagram).
The segment and backplane drivers each consist of a
CMOS inverter, with the N-Channel and P-Channel devices
ratioed to provide identical on resistances, and thus equal
rise and fall times. This eliminates any DC component which
could arise from differing rise and fall times, and ensures
maximum display life.
The backplane output can be disabled by connecting the
OSCILLATOR input (pin 36) to VSS. This synchronizes the
29 segment outputs directly with a signal input at the BP ter-
minal (pin 5) and allows cascading of several slave devices
to the backplane output of one master device. The back-
plane may also be derived from an external source. This
allows the use of displays with characters in multiples of four
and a single backplane. A slave device will represent a load
of approximately 200pF (comparable to one additional seg-
ment). The limitation on the number of devices that can be
slaved to one master device backplane driver is the addi-
tional load represented by the larger backplane of displays
of more than four digits, and the effect of that load on the
backplane rise and fall times. A good rule of thumb to
observe in order to minimize power consumption, is to keep
the rise and fall times less than about 5 microseconds. The
backplane driver of one device should handle the back-plane
to a display of 16 one-half-inch characters without the rise
and fall times exceeding 5µs (i.e., 3 slave devices and the
display backplane driven by a fourth master device). It is rec-
ommended that if more than four devices are to be slaved
together, that the backplane signal be derived externally and
all the lCM7224 devices be slaved to it.
This external backplane signal should be capable of driving
very large capacitive loads with short (1-2µs) rise and fall
times. The maximum frequency for a backplane signal
should be about 150Hz, although this may be too fast for
optimum display response at lower display temperatures,
depending on the display used.
The onboard oscillator is designed to free run at approximately
19kHz, at microampere power levels. The oscillator frequency
is divided by 126 to provide the backplane frequency, which
will be approximately 150Hz with the oscillator free-running.
The oscillator frequency may be reduced by connecting an
external capacitor between the OSCillator terminal (pin 36)
and VDD; see the plot of oscillator/back-plane frequency in
“Typical Performance Curves” for detailed information.
The oscillator may also be overdriven if desired, although
care must be taken to insure that the backplane driver is not
disabled during the negative portion of the overdriving signal
(which could cause a DC component to the display). This
can be done by driving the OSCILLATOR input between the
positive supply and a level out of the range where the back-
plane disable is sensed, about one fifth of the supply voltage
above the negative supply. Another technique for overdriv-
ing the oscillator (with a signal swinging the full supply) is to
skew the duty cycle of the overdriving signal such that the
negative portion has a duration shorter than about one
microsecond. The backplane disable sensing circuit will not
respond to signals of this duration.
Counter Section
The lCM7224 implements a four-digit ripple carry resettable
counter, including a Schmitt trigger on the COUNT input and
a CARRY output. Also included is an extra D-type flip-flop,
clocked by the CARRY signal which controls the half-digit
segment driver. This output driver can be used as either a
true half-digit or as an overflow indicator. The counter will
increment on the negative-going edge of the signal at the
COUNT input, while the CARRY output provides a negative-
going edge following the count which increments the counter
from 9999 to 10000. Once the half-digit flip-flop has been
clocked, it can only be reset (with the rest of the counter) by
a negative level at the RESET terminal, pin 33. However, the
four decades will continue to count in a normal fashion after
the half-digit is set, and subsequent CARRY outputs will not
be affected.
A negative level at the COUNT INHIBIT input disables the
first divide-by-two in the counter chain without affecting its
clock. This provides a true inhibit, not sensitive to the state of
the COUNT input, which prevents false counts that can
result from using a normal logic gate to prevent counting.
Each decade of the counter directly drives a four-to-seven
segment decoder which develops the required output data.
The output data is latched at the driver. When the STORE
pin is low, these latches are updated, and when it is high or
floating, the latches hold their contents.
The decoders also include zero detect and blanking logic to
provide leading zero blanking. When the Leading Zero
Blanking INput is floating or at a positive level, this circuitry is
enabled and the device will blank leading zeroes. When it is
low, or the half-digit is set, leading zero blanking is inhibited,
and zeroes in the four digits will be displayed. The Leading
Zero Blanking OUTput is provided to allow cascaded
devices to blank leading zeroes correctly. This output will
assume a positive level only when all four digits are blanked;
this can only occur when the Leading Zero Blanking INput is
at a positive level and the half-digit is not set.
For example, in an eight-decade counter with overflow using
two lCM7224 devices, the Leading Zero Blanking OUTput of
the high order digit would be connected to the Leading Zero
Blanking INput of the low order digit device. This will assure
correct leading zero blanking for all eight digits.
The STORE, RESET, COUNT INHIBIT, and Leading Zero
Blanking INputs are provided with pullup devices, so that
they may be left open when a positive level is desired. The
CARRY and Leading Zero Blanking OUTputs are suitable for
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ICM7224.PDF ] | |
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