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PDF KMM372F1600BK Data sheet ( Hoja de datos )

Número de pieza KMM372F1600BK
Descripción DRAM Module
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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No Preview Available ! KMM372F1600BK Hoja de datos, Descripción, Manual

DRAM MODULE
KMM372F160(8)0BK/BS
KMM372F160(8)0BK/BS EDO Mode
16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM372F160(8)0B is a 16Mx72bits Dynamic
RAM high density memory module. The Samsung
KMM372F160(8)0B consists of eighteen CMOS 16Mx4bits
DRAMs in SOJ/TSOP-II 400mil packages and two 16 bits
driver IC in TSSOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM372F160(8)0B is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
tHPC
-5
50ns
18ns
84ns
20ns
-6
60ns
20ns
104ns
25ns
FEATURES
• Part Identification
Part number
PKG Ref. CBR Ref. ROR Ref.
KMM372F1600BK SOJ
4K
KMM372F1600BS TSOP
4K/64ms
KMM372F1680BK SOJ
8K
KMM372F1680BS TSOP
4K/64ms
8K/64ms
• Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(1250mil), double sided component
PIN CONFIGURATIONS
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Names
Function
1 VSS 29 *CAS2 57 DQ22 85 VSS 113 *CAS3 141 DQ58
2 DQ0 30 RAS0 58 DQ23 86 DQ36 114 *RAS1 142 DQ59
3 DQ1 31 OE0 59 VCC 87 DQ37 115 RFU 143 VCC
4 DQ2 32 VSS 60 DQ24 88 DQ38 116 VSS 144 DQ60
5 DQ3 33 A0 61 RFU 89 DQ39 117 A1 145 RFU
6 VCC 34 A2 62 RFU 90 VCC 118 A3 146 RFU
7 DQ4 35 A4 63 RFU 91 DQ40 119 A5 147 RFU
8 DQ5 36 A6 64 RFU 92 DQ41 120 A7 148 RFU
9 DQ6 37 A8 65 DQ25 93 DQ42 121 A9 149 DQ61
10 DQ7 38 A10 66 DQ26 94 DQ43 122 A11 150 DQ62
11 DQ8 39 A12 67 DQ27 95 DQ44 123 *A13 151 DQ63
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 RFU 69 DQ28 97 DQ45 125 RFU 153 DQ64
14 DQ10 42 RFU 70 DQ29 98 DQ46 126 B0 154 DQ65
15 DQ11 43 VSS 71 DQ30 99 DQ47 127 VSS 155 DQ66
16 DQ12 44 OE2 72 DQ31 100 DQ48 128 RFU 156 DQ67
17 DQ13 45 RAS2 73 VCC 101 DQ49 129 *RAS3 157 VCC
18 VCC 46 CAS4 74 DQ32 102 VCC 130 *CAS5 158 DQ68
19 DQ14 47 *CAS6 75 DQ33 103 DQ50 131 *CAS7 159 DQ69
20 DQ15 48 W2 76 DQ34 104 DQ51 132 PDE 160 DQ70
21 DQ16 49 VCC 77 DQ35 105 DQ52 133 VCC 161 DQ71
22 DQ17 50 RSVD 78 VSS 106 DQ53 134 RSVD 162 VSS
23 VSS 51 RSVD 79 PD1 107 VSS 135 RSVD 163 PD2
24 RSVD 52 DQ18 80 PD3 108 RSVD 136 DQ54 164 PD4
25 RSVD 53 DQ19 81 PD5 109 RSVD 137 DQ55 165 PD6
26 VCC 54 VSS 82 PD7 110 VCC 138 VSS 166 PD8
27 W0 55 DQ20 83 ID0 111 RFU 139 DQ56 167 ID1
28 CAS0 56 DQ21 84 VCC 112 *CAS1 140 DQ57 168 VCC
NOTE : A12 is used for only KMM372F1680BK/BS (8K Ref.)
A0, B0, A1 - A11 Address Input(4K ref.)
A0, B0, A1 - A12 Address Input(8K ref.)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0, RAS2
Row Address Strobe
CAS0, CAS4
Column Address Strobe
VCC Power(+3.3V)
VSS Ground
NC No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
Pins marked¡®*¡¯are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
50NS
1
1
1
1
1
0
0
0
60NS
1
1
1
1
1
1
1
0
ID0 0
PD Note :PD & ID Terminals must each be pulled up through a register to V CC at the next higher
ID1
0
level assembly. PDs will be either open (NC) or driven to V SS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to V SS without a buffer.
ID : 0 for Vss & 1 for N.C
0
0

1 page




KMM372F1600BK pdf
DRAM MODULE
KMM372F160(8)0BK/BS
AC CHARACTERISTICS (0°CTA70°C, VCC=3.3V±0.3V. See notes 1,2.)
Parameter
Column address to W delay time
CAS precharge time to W delay time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper page cycle time
Hyper page read-modify-write cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Output data hold time(C-B-R refresh)
Output buffer turn off delay time from RAS
Output buffer turn off delay time from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width (Hyper page cycle)
Symbol
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
tRASP
tRHCP
tWRP
tWRH
tOEA
tOED
tOEZ
tOEH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
-5
Min Max
45
47
10
8
3
33
20
70
7
50 200K
35
15
8
18
15
8 18
5
10
3 13
8 18
20
5
5
5
5
Present Detect Read Cycle
PDE to Valid PD bit
PDE to PD bit Inactive
tPD 10
tPDOFF
2
7
-6
Min Max
53
58
10
8
3
40
25
77
10
60 200K
40
15
8
20
18
8 18
5
10
3 13
8 18
20
5
5
5
5
10
27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
7
13
13
13
3,13
12
12
13
13
13
13
13
13
13
6,11
6,13
13

5 Page





KMM372F1600BK arduino
DRAM MODULE
HYPER PAGE READ CYCLE
KMM372F160(8)0BK/BS
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
tRASP
tCRP
tCSH
tRCD
tHPC
tCP
tCAS
¡ó
tHPC
tCAS
tCP
tHPC
tCP
tCAS
tRHCP
tCAS
tRAD
tASR tRAH tASC tCAH tASC tCAH tASC tCAH tASC tCAH
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
tRP
tREZ
VIH -
W
VIL -
VIH -
OE
VIL -
VOH -
DQ
VOL -
tRCS
tCAC
tAA
tCPA
tAA tCAC
tOEA
tRAC
tCAC
tDOH
VALID
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
tCAC
tAA
tCPA
tOCH
tOEA
tRCH
tRRH
tCPA
tCAC
tAA
tCHO
tOEP
tOEP
tOEZ
tOEZ
tOEA
VALID
DATA-OUT
tOEZ
VALID
DATA-OUT
Dont care
Undefined

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