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PDF KMM372V803BS Data sheet ( Hoja de datos )

Número de pieza KMM372V803BS
Descripción DRAM Module
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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DRAM MODULE
KMM372V80(8)3BK/BS
KMM372V80(8)3BK/BS Fast Page Mode
8Mx72 DRAM DIMM with ECC Using 8Mx8, 4K & 8K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM372V80(8)3B is a 8Mx72bits Dynamic
RAM high density memory module. The Samsung
KMM372V80(8)3B consists of nine CMOS 8Mx8bits DRAMs
in SOJ/TSOP-II 400mil packages and two 16 bits driver IC in
TSSOP package mounted on a 168-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The
KMM372V80(8)3B is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
PERFORMANCE RANGE
Speed
-5
tRAC
50ns
tCAC
18ns
tRC
90ns
tPC
35ns
-6
60ns
20ns
110ns
40ns
FEATURES
• Part Identification
Part number
PKG Ref. CBR Ref. ROR Ref.
KMM372V803BK
KMM372V803BS
SOJ
TSOP
4K
4K/64ms
KMM372V883BK
KMM372V883BS
SOJ
TSOP
8K
4K/64ms
8K/64ms
• Fast Page Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(1250mil), single sided component
PIN CONFIGURATIONS
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Names
Function
1 VSS 29 *CAS2 57 DQ22 85 VSS 113 *CAS3 141 DQ58
2 DQ0 30 RAS0 58 DQ23 86 DQ36 114 *RAS1 142 DQ59
3 DQ1 31 OE0 59 VCC 87 DQ37 115 RFU 143 VCC
4 DQ2 32 VSS 60 DQ24 88 DQ38 116 VSS 144 DQ60
5 DQ3 33 A0 61 RFU 89 DQ39 117 A1 145 RFU
6 VCC 34 A2 62 RFU 90 VCC 118 A3 146 RFU
7 DQ4 35 A4 63 RFU 91 DQ40 119 A5 147 RFU
8 DQ5 36 A6 64 RFU 92 DQ41 120 A7 148 RFU
9 DQ6 37 A8 65 DQ25 93 DQ42 121 A9 149 DQ61
10 DQ7 38 A10 66 DQ26 94 DQ43 122 A11 150 DQ62
11 DQ8 39 A12 67 DQ27 95 DQ44 123 *A13 151 DQ63
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 RFU 69 DQ28 97 DQ45 125 RFU 153 DQ64
14 DQ10 42 RFU 70 DQ29 98 DQ46 126 B0 154 DQ65
15 DQ11 43 VSS 71 DQ30 99 DQ47 127 VSS 155 DQ66
16 DQ12 44 OE2 72 DQ31 100 DQ48 128 RFU 156 DQ67
17 DQ13 45 RAS2 73 VCC 101 DQ49 129 *RAS3 157 VCC
18 VCC 46 CAS4 74 DQ32 102 VCC 130 *CAS5 158 DQ68
19 DQ14 47 *CAS6 75 DQ33 103 DQ50 131 *CAS7 159 DQ69
20 DQ15 48 W2 76 DQ34 104 DQ51 132 PDE 160 DQ70
21 DQ16 49 VCC 77 DQ35 105 DQ52 133 VCC 161 DQ71
22 DQ17 50 RSVD 78 VSS 106 DQ53 134 RSVD 162 VSS
23 VSS 51 RSVD 79 PD1 107 VSS 135 RSVD 163 PD2
24 RSVD 52 DQ18 80 PD3 108 RSVD 136 DQ54 164 PD4
25 RSVD 53 DQ19 81 PD5 109 RSVD 137 DQ55 165 PD6
26 VCC 54 VSS 82 PD7 110 VCC 138 VSS 166 PD8
27 W0 55 DQ20 83 ID0 111 RFU 139 DQ56 167 ID1
28 CAS0 56 DQ21 84 VCC 112 *CAS1 140 DQ57 168 VCC
NOTE : A12 is used for only KMM372V883BK/BS (8K Ref.)
A0, B0, A1 - A11 Address Input(4K ref.)
A0, B0, A1 - A12 Address Input(8K ref.)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0, RAS2
Row Address Strobe
CAS0, CAS4
Column Address Strobe
VCC Power(+3.3V)
VSS Ground
NC No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
Pins marked¡®*¡¯are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
50NS
1
0
1
1
0
0
0
0
60NS
1
0
1
1
0
1
1
0
PD Note :PD & ID Terminals must each be pulled up through a register to V CC at the next higher
ID0
ID1
0
0
level assembly. PDs will be either open (NC) or driven to V SS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to V SS without a buffer.
ID : 0 for Vss & 1 for N.C
0
0

1 page




KMM372V803BS pdf
DRAM MODULE
KMM372V80(8)3BK/BS
AC CHARACTERISTICS (0°CTA70°C, VCC=3.3V±0.3V. See notes 1,2.)
Parameter
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Fast page mode cycle time
Fast page mode read-modify-write cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Symbol
tCSR
tCHR
tRPC
tCPA
tPC
tPRWC
tCP
tRASP
tRHCP
tWRP
tWRH
tOEA
tOED
tOEZ
tOEH
-5
Min Max
10
8
3
35
35
76
10
50 200K
35
15
8
18
18
5 18
13
Present Detect Read Cycle
PDE to Valid PD bit
PDE to PD bit Inactive
tPD
tPDOFF
10
27
-6
Min Max
10
8
3
40
40
85
10
60 200K
40
15
8
20
20
5 20
15
10
27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
11
11
11
3,11
11
11
11
11
11
11
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If tWCStWCS(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If tRWDtRWD(min),
tCWDtCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in
early write cycles.
5. Assumes tha tRCDtRCD(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
10. Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
11. The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.

5 Page





KMM372V803BS arduino
DRAM MODULE
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
KMM372V80(8)3BK/BS
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
VIH -
DQ
VIL -
tRASP
tRHCP
¡ó
tCRP
tASR
tRCD
tRAD
tASC
tRAH
tPC
tCAS
tCSH
tCAH
ROW
ADDR
COLUMN
ADDRESS
tPC
tCP tCP
tCAS
¡ó
tRSH
tCAS
tASC tCAH
COLUMN
ADDRESS
tASC tCAH
¡ó
COLUMN
¡ó ADDRESS
tWCS
tWCH
tWP
tWCS
tWCH tWCS
¡ó
tWP
tWCH
tWP
tCWL
tDS tDH
VALID
DATA-IN
tCWL
¡ó
tCWL
tRWL
¡ó
tDS tDH
VALID
DATA-IN
¡ó
¡ó
tDS tDH
VALID
DATA-IN
tRP
Dont care
Undefined

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