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PDF KS0068B Data sheet ( Hoja de datos )

Número de pieza KS0068B
Descripción 16COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! KS0068B Hoja de datos, Descripción, Manual

KS0068B
16COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
100 QFP
The KS0068B is a dot matrix LCD driver & controller LSl which is
fabricated by low power CMOS technology.
FUNCTION
Character type dot matrix LCD driver & controller
Internal driver: 16 common and 60 segment signal output.
Display character format; 5 7 dots + cursor, 5 10 dots + cursor
Easy interface with a 4-bit or 8-bit MPU
Display character pattern:
5 7 dots format: 192 kinds, 5 10 dots format: 32kinds
The special character pattern can be programmable by
Character Generator RAM directly.
A customer character pattern can be programmable by mask
option (KS0068B-00; Standard type)
KS0068B-00
English, Japanese
Numberal
Automatic power on reset function.
It can drive a maximum 80 characters by using the kS0065B
or KS0063B, KS0068B externally.
It is possible to read both Character Generator and Display
Data RAM from MPU.
FEATURES
Internal Memory
- Character Generator ROM: 8320bits
- Character Generator RAM: 512 bits
- Display Data RAM: 80 8bits for 80 digits.
Power Supply Voltage; +5Vä10%, +3Vä10%
Supply voltage for display: 0~-5V(V5)
CMOS process
1/8 duty, 1/11 duty or 1/16 duty: selectable
(1/8 duty; 5 7 dots format 1 line, 1/11 duly; 5 x 10 dots format I line,
1/16 duty: 5 7 dots format 2 line)
100 QFP or bare chip available.

1 page




KS0068B pdf
KS0068B
16COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Internal logic of input/output terminal
Input/Output
Input
No
Pull
up
Logic diagram
Applicable pin
E
with
pull
up
Output
RS, R/W
CLK1, CLK2
M,D
Input
Output
DB0-DB7

5 Page





KS0068B arduino
KS0068B
16COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(3) Interface mode with KS0065B, KS0063B
Characteristic
Symbol
Min
Typ
Max
Unit
Clock Pulse Width High
tWCKH
800
-
- ns
Clock Pulse Width Low
tWCKL
800
-
- ns
Data Set-Up Time
tSU 300
-
- ns
Data Hold Time
tDH 300
-
- ns
Clock Set-Up Time
tCSU 500
-
- ns
M Delay Time
tDM -1000
-
1000
ns
Test pin
CLK
CLK
D
D
CLK
M
C LK 1
C LK 2
D
M
0 .9 V D D
0 .9 V D D
0 .1 V D D
tW C K H
tC S U
0 .9 V D D
tC S U
tW C K H
0 .1 V D D
0 .9 V D D
tW C K L
0 .1 V D D
0 .9 V D D
0 .1 V D D
tS U
0 .9 V D D
0 .1 V D D
tD H
0 .9 V D D
tD M

11 Page







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