|
|
PDF ICS9248-87 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-87 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS9248-87 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
Integrated
Circuit
Systems, Inc.
ICS9248-87
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Output Features:
• 2- CPUs @2.5V, up to 155MHz.
• 9 - SDRAM @ 3.3V, up to 155MHz.
• 8 - PCICLK @ 3.3V
• 1 - IOAPIC @ 2.5V,
• 2 - 3V66MHz @ 3.3V
• 2- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V
• 1- REF @3.3V, 14.318MHz.
Features:
• Up to 155MHz frequency support
• Support FS0-FS3 strapping status bit for I2C read back.
• Support power management: Power down Mode from I2C
programming.
• Spread spectrum for EMI control ( ± 0.25% center).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU – CPU: <175ps
• SDRAM - SDRAM: < 250ps
• 3V66 – 3V66: <175ps
• PCI – PCI: <500ps
• For group skew specification, please refer to group
timing relationships table.
Pin Configuration
48-Pin 300mil SSOP
*: These inputs have a 120K pull up to VDD.
1: These are double strength.
Block Diagram
Functionality
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SEL24_48#
{I2C
SDATA
SCLK
FS[3:0]
PD#
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
2
24_48MHz
REF1
CPUCLK [1:0]
2
SDRAM [7:0]
8
SDRAM_F
IOAPIC
PCICLK [7:0]
8
3V66 [1:0]
2
FS3 FS2 FS1 FS0
0000
0001
00 10
00 11
0 100
0 10 1
0 110
0111
10 0 0
100 1
10 10
10 11
1100
110 1
1 1 10
1111
CPU CPU/ SDRAM
(MHz) SDRAM (MHz)
83.3
124.00
155.00
143.96
70.00
112.00
150.00
140.00
68.33
107.00
138.00
137.33
66.80
100.30
133.60
133.60
1.00 83.3
1.00 124.00
1.00 155.00
1.33 108.00
0.67 105.00
1.00 112.00
1.00 150.00
1.33 105.00
0.67 102.50
1.00 107.00
1.00 138.00
1.33 103.00
0.67 100.20
1.00 100.30
1.00 133.60
1.33 100.20
3V66
(MHz)
PCICLK
(3V66*
1/2)
(MHz)
IOAPIC
(PCI*
1/2)
(MHz)
IOAPIC
(PCI)
(MHz)
55.48 27.74 13.87 27.74
82.67 41.33 20.67 41.33
103.33 51.67 25.83 51.67
72.00 36.00 18.00 36.00
70.00 35.00 17.50 35.00
74.67 37.33 18.67 37.33
100.00 50.00 25.00 50.00
70.00 35.00 17.50 35.00
68.33 34.17 17.08 34.17
71.33 35.67 17.83 35.67
92.00 46.00 23.00 46.00
68.67 34.34 17.17 34.34
66.80 33.40 16.70 33.40
66.80 33.40 16.70 33.40
89.07 44.53 22.27 44.53
66.80 33.40 16.70 33.40
9248-87 Rev D 10/27/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
1 page  
ICS9248-87
Preliminary Product Preview
Byte 0: Control Register Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
0 Reserved
Bit5 -
0 Reserved
Bit4 -
0 Reserved
Bit3 -
0 Reserved
Bit2 23 1 24/48MHz
Bit1 21,22 1 48MHz
Bit0 -
0 Reserved
Byte 1: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 32
1 SDRAM7
Bit6 33
1 SDRAM6
Bit5 35
1 SDRAM5
Bit4 36
1 SDRAM4
Bit3 37
1 SDRAM3
Bit2 39
1 SDRAM2
Bit1 40
1 SDRAM1
Bit0 41
1 SDRAM0
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 19 1 PCICLK7
Bit6 18 1 PCICLK6
Bit5 17 1 PCICLK5
Bit4 15 1 PCICLK4
Bit3 14 1 PCICLK3
Bit2 12 1 PCICLK2
Bit1 11 1 PCICLK1
Bit0 10 1 PCICLK0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
0 Reserved
Bit5 -
0 Reserved
Bit4 -
0 Reserved
Bit3 -
0 Reserved
Bit2 -
0 Reserved
Bit1 -
0 Reserved
Bit0 -
0 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
3. SDRAM_F is free running and cannot be turned off by I2C
Byte 3: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
X FS2#
Bit5 -
X FS1#
Bit4 -
X FS0#
Bit3 -
1 IOAPIC
Bit2 -
Bit1 -
Bit0 -
X (SEL24_48#)#
FREQ_IOAPIC
1
=1=>IOAPIC=PCICLK/2
FREQ_IOAPIC=0=>
IOAPIC= PCICLK
X FS3#
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Dont write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-87
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
Output Impedance
RDSP4B1 VO = VDD*(0.5)
Output Impedance RDSN4B1 VO = VDD*(0.5)
Output High Voltage VOH4\B IOH = -5.5 mA
Output Low Voltage VOL4B IOL = 9.0 mA
Output High Current
IOH4B VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
Output Low Current
IOL4B VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V
Rise Time
tr4B1 VOL = 0.4 V, VOH = 2.0 V
Fall Time
tf4B1 VOH = 2.0 V, VOL = 0.4 V
Duty Cycle
dt4B1 VT = 1.25 V
Jitter
Skew
tjcyc-cyc
Tsk41
VT = 1.25 V
1Guarenteed by design, not 100% tested in production.
MIN TYP MAX UNITS
9 30 Ω
9 30 Ω
2V
0.4 V
-27 -27 mA
27 30 mA
0.4 1.6 ns
0.4 1.6 ns
45 55 %
500 ps
250 ps
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
RDSP31
RDSN31
VOH3
VOL3
IOH3
IOL3
Tr31
Tf31
Dt31
Tsk31
tjcyc-cyc
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
10
10
2.4
-54
54
0.4
0.4
45
24 Ω
24 Ω
V
0.4 V
-46 mA
53 mA
1.6 ns
1.6 ns
55 %
250 ps
250 ps
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-87.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS9248-80 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-81 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-87 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |