|
|
PDF ICS9248-96 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-96 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS9248-96 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
Integrated
Circuit
Systems, Inc.
ICS9248-96
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Output Features:
• 2- CPUs @ 2.5V, up to 155MHz.
• 9 - SDRAM @ 3.3V, up to 155MHz including
1 free running
• 8 - PCICLK @ 3.3V
• 1 - IOAPIC @ 2.5V,
• 2 - 3V66MHz @ 3.3V, 2X PCI MHz
• 2 - 48MHz, @ 3.3V fixed.
• 1 - 24/48MHz, @3.3V selectable by I2C
• 1 - REF @v3.3V, 14.318MHz.
Features:
• Up to 157MHz frequency support
• Support FS0-FS3 strapping status bit for I2C read back.
• Support power management: Through Power down
Mode from I2C programming.
• Spread spectrum for EMI control ( ± 0.25% center).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU – CPU: <175ps
• SDRAM - SDRAM: < 250ps
• 3V66 – 3V66: <175ps
• PCI – PCI: <500ps
• CPU-SDRAM<500ps
• For group skew specifications, please refer to group
timing relationship.
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
** 60K pull-up to VDD on indicated input
1 These are double strength.
Block Diagram
9248- 96 Rev A 2/7/00
Third party brands and names are the property of their respective owners.
Functionality
FS3 FS2 FS1 FS0
000 0
000 1
0010
001 1
0 10 0
0 10 1
0 110
0 11 1
100 0
100 1
10 10
10 1 1
1 10 0
1 10 1
1110
111 1
CPU SDRAM
(MHz) (MHz)
66.80
68.00
100.30
103.00
133.73
145.00
133.73
137.33
140.00
140.00
118.00
124.00
133.70
137.00
150.00
72.50
100.20
102.00
100.30
103.00
100.30
108.75
100.30
103.00
105.00
140.00
118.00
124.00
133.70
137.00
112.50
108.75
3V66
(MHz)
66.80
68.00
66.87
68.67
66.87
72.50
66.87
68.67
70.00
93.33
78.67
82.67
89.13
91.33
75.00
72.50
PCICLK
(MHz)
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
IOAPIC
1=PCICLK/2
(MHz)
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
IOAPIC
0=PCICLK
(MHz)
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
Additional frequencies selectable through I2C programming.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
1 page  
ICS9248-96
Preliminary Product Preview
Byte 1: Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
28
27
26
-
31
PWD
DESCRIPTION
X FS3#
X FS0#
X FS2#
1 24_48MHz
1 48MHz_1
1 48MHz_0
1 (Reserved)
1 SDRAM_F
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
20
19
17
16
15
13
12
11
PWD
DESCRIPTION
1 PCICLK7
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 32
1 SDRAM7
Bit 6 33
1 SDRAM6
Bit 5 35
1 SDRAM5
Bit 4 36
1 SDRAM4
Bit 3 37
1 SDRAM3
Bit 2 39
1 SDRAM2
Bit 1 40
1 SDRAM1
Bit 0 41
1 SDRAM0
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 (Reserved)
Bit 6 8
1 3V66_1
Bit 5 7
1 3V66_0
Bit 4 -
X FREQ_IOAPIC#
Bit 3 46
1 IOAPIC
Bit 2 -
X FS1#
Bit 1 44
1 CPUCLK1
Bit 0 45
1 CPUCLK0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
1 Reserved
Bit6 -
1 Reserved
Bit5 -
1 Reserved
Bit4 -
1 Reserved
Bit3 -
1 Reserved
Bit2 -
1 Reserved
Bit1 -
1 Reserved
Bit0 -
1 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Dont write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-96
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance
Output Impedance
Output High Voltage
RDSP11
RDSN11
VOH1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
12 55 Ω
12 55 Ω
2.4 V
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
VOL1
IOH1
IOL1
tr11
tf11
dt11
tsk11
tjcyc-cyc
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
0.5
0.5
45
0.55 V
-33 mA
38 mA
2 ns
2 ns
55 %
500 ps
500 ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance
Output Impedance
RDSP51
RDSN51
VO = VDD*(0.5)
VO = VDD*(0.5)
20 60 Ω
20 60 Ω
Output High Voltage VOH5 IOH = 1 mA
2.4 V
Output Low Voltage
VOL5 IOL = -1 mA
0.4 V
Output High Current
IOH5 VOH@MIN=1 V, VOH@MAX= 3.135 V
-29
-23 mA
Output Low Current
Rise Time
Fall Time
Duty Cycle
Jitter
IOL5
tr51
tf51
dt51
tjcyc-cyc1
tjcyc-cyc1
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
29 27 mA
1.8 4 nS
1.7 4 nS
45 55 %
500 pS
1000 pS
Skew
Tsk VT = 1.5 V
250 pS
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-96.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS9248-90 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-92 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-96 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-97 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |