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PDF ICS9248-97 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-97 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-97
Frequency Timing Generator for PENTIUM II Systems
RecommendedApplication:
Camino chipset
Output Features:
3 - CPUs @ 2.5V, up to 180MHz.
3 - IOAPIC @ 2.5V, PCI/2
3 - 3V66MHz @ 3.3V.
11 - PCIs @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz, @ 3.3V
1 - CPU/2, @ 2.5V.
Features:
Up to 180MHz frequency support
Support power management: Power down Mode
from I2C programming.
Spread spectrum for EMI control
± 0.25% center spread).
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Pin Configuration
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GNDPCI
*FS0/PCICLK_F
*FS1/PCICLK0
VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PCICLK7
PCICLK8
PCICLK9
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDLAPIC
47 IOAPIC0
46 IOAPIC1
45 GNDLAPIC
44 IOAPIC2
43 VDDLCPU/2
42 CPU/2
41 GNDLCPU/2
40 CPUCLK0
39 VDDLCPU
38 CPUCLK1
37 CPUCLK2
36 GNDLCPU
35 VDD66
34 3V66_0
33 3V66_1
32 3V66_2
31 GND66
30 SDATA
29 SCLK
28 VDD48
27 48MHz/FS4*
26 24_48MHz
25 GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SEL24_48#
SDATA
SCLK
FS (4:0)
PD#
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
/2
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF (1:0)
CPUCLK (2:0)
CPU/2
IOAPIC (2:0)
PCICLK (9:0)
PCICLK_F
3V66 (2:0)
9248-97 Rev E 08/18/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-97
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
38
37
42
47
46
44
-
PWD
1
1
1
1
1
1
1
X
Description
CPUCLK 0
CPUCLK 1
CPUCLK 2
CPU/2
IOAPIC0
IOAPIC1
IOAPIC2
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
18
17
15
14
12
11
9
8
PWD
1
1
1
1
1
1
1
1
Description
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
33
32
-
3
2
-
-
PWD
1
1
1
X
1
1
X
X
Description
3V66_0
3V66_1
3V66_2
FS1#
REF1
REF0
FS3#
FS2#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
26
27
-
-
22
21
20
-
PWD
1
1
X
1
1
1
1
X
Description
24_48MHz
48MHz
FS0#
(Reserved)
PCICLK9
PCICLK8
PCICLK7
FS4#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin #
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte6: Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin #
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
1
1
0
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Note: Dont write into this register, writing into this register
can cause malfunction
5
5 Page 
ICS9248-97
Power Management Features:
PD# CPUCLK CPU/2 IOAPIC 3V66
0 LOW LOW LOW LOW
PCI
PCI_F
REF.
48MHz
Osc
LOW LOW LOW OFF
VCOs
OFF
1 ON ON ON ON ON ON ON ON ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Signal
PD#
Signal State
1 (normal operation)
0 (power down)
Latency
No. of rising edges of
PCICLK
3mS
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-97.PDF ] | |
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