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PDF ICS9248-168 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-168 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS9248-168 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9248-168
AMD - K7™ Clock Generator for Mobile System
Recommended Application:
VIA KT133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 7 - SDRAM @ 3.3V
• 8 - PCI @ 3.3V,
• 1 - 48MHz, @ 3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 3 - REF @ 3.3V, 14.318MHz.
Features:
• Up to 153MHz frequency support
• Support power management: CPU stop and Power down
Mode from I2C programming.
• Spread spectrum for EMI control
(± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down
spread).
• Uses external 14.318MHz crystal
Pin Configuration
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF01
REF1
REF2
GND
GND
VDD
CPUCLK2
CPUCLKT02
CPUCLKC02
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
1 These outputs have double strength to drive 2 loads.
2 These outputs can be set to 1.5X strength through I2C
Block Diagram
PLL2
X1
X2
SEL24_48#
SDATA
SCLK
FS (2:0)
PD#
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
PCI
DIVDER
Stop
SDRAM
DRIVER
Stop
Functionality
48MHz
24_48MHz
REF (2:0)
CPUCLK
CPUCLKC0
CPUCLKT0
PCICLK (6:0)
PCICLK_F
SDRAM (5:0)
SDRAM_F
FS2 FS1 FS0 CPU PCI Spread Percentage
0 0 0 100.00 33.33 +/- 0.35% Center Spread
0 0 1 133.33 33.33 +/- 0.35% Center Spread
0 1 0 100.00 33.33 0 to - 0.5% Down Spread
0 1 1 133.33 33.33 0 to - 0.5% Down Spread
1 0 0 100.00 33.33 +/- 0.6% Center Spread
1 0 1 133.33 33.33 +/- 0.6% Center Spread
1 1 0 90.00 30.00 +/- 0.25% Center Spread
1 1 1 120.00 30.00 +/- 0.25% Center Spread
9248-168 Rev B 01/09/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-168
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
22
5
4
42
-
41, 40
-
42
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
FS0
FS1
FS2
CPUCLK 0=1.5X 1=1X
Reserved
CPUCLKT/C 0=1.5X 1=1X
Reserved
CPUCLK
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
4
15
12
11
10
9
8
5
PWD
DESCRIPTION
1 PCICLK_F
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
23
22
23
48
47
46
-
PWD
DESCRIPTION
1 Reserved
1 SEL24_48#
1 48MHz
1 24_48MHz
1 REF0
1 REF1
1 REF2
1 Reserved
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
27
28
29
32
33
36
37
PWD
DESCRIPTION
1 Reserved
1 SDRAM_F
1 SDRAM5
1 SDRAM4
1 SDRAM3
1 SDRAM2
1 SDRAM1
1 SDRAM0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
- 1 Reserved
- 1 Reserved
- 1 Reserved
- 1 Reserved
- 1 Reserved
- 1 Reserved
- 1 Reserved
- 1 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
0 Reserved
Bit 6 -
0 Reserved
Bit 5 -
0 Reserved
Bit 4 -
0 Reserved
Bit 3 -
0 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
0 Reserved
Note: Don’t write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-168
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248-
168 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Fig. 1
Third party brands and names are the property of their respective owners.
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-168.PDF ] | |
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