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PDF ICS9248-65 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-65 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-65
Frequency Timing Generator for PENTIUM IISystems
Features
Generates the following system clocks:
- 3 CPU clocks ( 2.5V, 100/133MHz)
- 10 PCI clocks, including 1 free-running
(3.3V, 33.3MHz)
- 1 CPU/2 clocks (2.5V, 50/66.6MHz)
- 1 IOAPIC clocks (2.5V, 16.67MHz)
- 3 Fixed frequency 66MHz clocks(3.3V, 66.6MHz)
- 2 REF clocks(3.3V, 14.318MHz)
- 1 USB clock (3.3V, 48MHz)
Efficient power management through PD#.
0 to -0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
Uses external 14.318MHz crystal.
Key Specification
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
PCI Output Jitter. <500ps
Ref Output Jitter. <1000ps
CPU 0:2 Output Skew: <175ps
PCI_F, PCI 1:7 Output Skew: <500ps
3V66_0:2 Output Skew <250ps
CPU to 3V66_0:2 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4ns (CPU leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Block Diagram
Pin Configuration
Third party brands and names are the property of their respective owners.
9248-65 Rev C 7/28/99
48-pin SSOP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-65
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Offset
Group
Offset
CPU to 3V66
0.0-1.5ns CPU leads
3V66 to PCI
1.5-4.0ns 3V66 leads
CPU to IOAPIC
1.5-4.0ns CPU leads
No te: 1 . All o ffsets are to be meas u red at ris in g edg es.
Measurement Loads
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
CPU @ 20pF, IOAPIC @ 20pF
Measure Points
CPU @1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU @1.25V, IOAPIC @ 1.5V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = VDDL = 3.3 V +/-5%, (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP 100
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 100 MHz
2
VSS-0.3
-5
-200
VDD+0.3
0.8
0.1 5
2.0
-100
65
V
V
µA
µA
µA
Operating
IDD3.3OP133 CL = 0 pF; Select @ 133.3 MHz
IDD3.3OP144 CL = 0 pF; Select @ 144 MHz
71
160 mA
75
Power Down
IDD3.3OP154 CL = 0 pF; Select @ 154 MHz
IDD3.3PD CL = 0 pF; PWRDWN# = 0
78
64 200 µA
Supply Current
Input frequency
Input Capacitance1
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
Skew1
Skew1
Fi
CIN
CINX
Ttrans
Ts
TSTAB
tCP U -P CI
tCP U -3 V6 6
t3 V6 6 -P CI
VDD = 3.3 V
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V; VTL = 1.25 V
VT = 1.5 V; VTL = 1.25 V
VT = 1.5 V
12 14.318 16
5
27 36 45
13
0.5
3
1.5 2.4
4
1.4 1.5
1.4 4
MHz
pF
pF
ms
ms
ms
ns
ns
ns
1Guaranteed by design, not 100% tested in production.
5
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| PDF Descargar | [ Datasheet ICS9248-65.PDF ] | |
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