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PDF ICS9248-66 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-66 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-66
Advance Information
Frequency Timing Generator for PENTIUM II Systems
Features
Generates the following system clocks:
- 3 CPU clocks ( 2.5V, 100/133MHz)
- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)
- 1 CPU/2 clocks (2.5V, 50/66MHz)
- 1 IOAPIC clocks (2.5V, 16.67MHz)
- 3 Fixed frequency 66MHz clocks(3.3V, 66MHz)
- 2 REF clocks(3.3V, 14.318MHz)
- 1 USB clock (3.3V, 48MHz)
Efficient power management through PD#, CPU_STOP#
and PCI_STOP#.
0 to -0.5% typical down spread modulation on CPU,
PCI, IOAPIC, 3V66 and CPU/2 output clocks.
Uses external 14.318MHz crystal.
Key Specification
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Block Diagram
Pin Configuration
9248-66 Rev - 7/28/99
48-pin SSOP
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
1 page  
ICS9248-66
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used
to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a
full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the
PCI outputs to become enabled/disabled.
Notes:
1. All timing is referenced to CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output.
3. Internal means inside the chip.
4. All other clocks continue to run undisturbed.
5. PD# and CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
5
5 Page 
ICS9248-66
Advance Information
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095 .101
.110
.008 .012
.016
.088 .090
.092
.008 .010
.0135
.005 -
.010
See Variations
.292 .296
.299
0.025 BSC
.400 .406
.410
.010 .013
.016
.024 .032
.040
See Variations
0° 5°
8°
.085 .093
.100
VARIATIONS
AD
MIN.
.720
D
NOM.
.725
MAX.
.730
N
56
56 Pin SSOP Package
Ordering Information
ICS9248yF-66
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products
11 in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
11 Page | ||
| Páginas | Total 11 Páginas | |
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