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PDF ICS9248-73 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-73 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248 - 73
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9248-73 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9248-73
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Block Diagram
Features
Generates the following system clocks:
- 2 - CPUs @ 2.5V , up to 150MHz.
- 1 - IOAPIC @ 2.5V, PCI/2MHz.
- 9 - SDRAMs @ 3.3V, up to 150MHz.
- 2 - 3V66 @ 3.3V, 2x PCI MHz.
- 8 - PCIs @ 3.3V.
- 2 - 48MHz, @ 3.3V fixed.
- 1 - REF @ 3.3V, 14.318MHz.
- 1 - 24_48MHz, @ 3.3V fixed.
Supports spread spectrum modulation ,
down spread 0 to -0.5%, ±0.25% center spread.
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Pin Configuration
Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9248-73 Rev B 2/10/00
48-Pin 300 mil SSOP
*120K ohm pull-up to VDD on indicated inputs.
**60K ohm pull-up to VDD on indicated inputs.
1. These pins will have 2x drive strength
Power Groups
GNDREF,VDDREF = REF & Crystal
GND3V66,VDD3V66 =3V66
GNDPCI, VDDPCI = PCICLK
GNDCOR, VDDCOR = PLL core
GND48,VDD48 =48MHz
GNDSDR, VDDSDR = SDRAM
GNDLCPU, VDDLCPU = CPUCLK
GNDAPIC, VDDAPIC = IOAPIC
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248 - 73
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-X
-X
-X
28 1
27 1
26 1
-0
31 1
Description
FS3#
FS0#
FS2#
24-48MHz
48MHz
48MHz
(Reserved)
SDRAM_F
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
32 1
33 1
35 1
36 1
37 1
39 1
40 1
41 1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
20 1
19 1
17 1
16 1
15 1
13 1
12 1
11 1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-0
71
81
-X
47 1
-X
44 1
45 1
Description
(Reserved)
3V66_0
3V66_1
SEL_3V66#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
5
5 Page 
ICS9248 - 73
Group Offset Waveforms
Group Skews at common Transition Edges
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
CL = 20 pF for CPU and IOAPIC
CL = 50 pF for PCI0 & PCI1, CL = 30 pF for other PCIs, SDRAM and 3V66
GROUP
SYMBOL
CONDITIONS
MIN TYP
CPU to SDRAM
tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V
SDRAM leads CPU by 2.5ns for CPU66
CPU leads SDRAM by 5.0ns for CPU100
0 100
CPU to 3V66
tCP U -3 V6 6
VT = 1.5 V; VTL = 1.25 V
CPU leads 3V66 by 7.5ns for CPU66
CPU leads 3V66 by 0.0ns for CPU100
0 100
IOAPIC to PCI
3V66 to PCI
tIOAPIC-PCI VT = 1.5 V; VTL = 1.25 V
t3V66-PCI VT = 1.5 V
0 360
1.5 2.5
Guaranteed by design, not 100% tested in production.
MAX UNITS
500 ps
500 ps
500 ps
4 ns
11
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| PDF Descargar | [ Datasheet ICS9248-73.PDF ] | |
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