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PDF ICS9248-127 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-127 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248 - 127
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9248-127 is the single chip clock solution for Desktop
designs using the VIA MVP4 and Aladdin 7 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
127 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Features
• Up to 124MHz frequency support.
• Spread Spectrum for EMI control 0 to -0.5% down
spread and ±0.25% center spread
• Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
• Provides the following system clocks
- 4-CPUs @ 3.3V, up to 124MHz.
- 13-SDRAMs @3.3V, up to 124MHz
(including SDRAM_F)
- 6-PCI (including 1 free running, PCICLK_F)
@3.3V, CPU/2 or CPU/3.
- 1-24MHz @3.3V fixed.
- 1-48MHz @3.3V fixed.
- 2-REF @3.3V, 14.318MHz.
• Efficient Power management scheme through PCI
and STOP CLOCKS.
Block Diagram
X1
X2
BUFFER IN
PLL2
XTAL
OSC
/2
FS(3:0)
4
MODE
CLK_STOP#
PCI_STOP#
SDATA
SCLK
PLL1
Spread
Spectrum
LATCH
POR
4
Control
Logic
Config.
Reg.
STOP
STOP
PCI
CLOCK
DIVDER
STOP
48MHz
24MHz
2 REF (1:0)
CPUCLK_F
3 CPUCLK (2:0)
12 SDRAM (11:0)
SDRAM_F
PCICLK (4:0)
5
PCICLK_F
Pin Configuration
VDDREF
*PCI_STOP#/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2*
47 VDDCPU
46 CPUCLK_F
45 CPUCLK0
44 GND
43 CPUCLK1
42 CPUCLK2
41 CLK_STOP#
40 GND
39 SDRAM_F
38 SDRAM0
37 SDRAM1
36 VDDSDR
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDSDR
29 SDRAM6
28 SDRAM7
27 VDD48
26 48MHz/FS0*
25 24MHz/FS1*
48-Pin SSOP
* Internal Pull-up Resistor of 240K to VDD
Power Groups
VDDCPU, GNDCPU = CPUCLKS, CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS, SDRAM_F
VDDPCI, GNDPCI = PCICLKS, PCICLK_F
VDD48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
9248-127 Rev C 8/18/00
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
46
-
-
39
42
43
45
PWD
X
1
1
1
1
1
1
1
Description
Latched FS2#
CPUCLK_F (Act/Inact)
(Reserved)
(Reserved)
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
X
1
1
1
1
1
1
1
Description
Latched FS0#
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
ICS9248 - 127
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
17
18
20
21
28
29
31
32
PWD
1
1
1
1
1
1
1
1
Description
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
5 Page 
ICS9248 - 127
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248-
127 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
11 Page | ||
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