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PDF ICS9248-128 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-128 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-128
Frequency Generator & Integrated Buffers
Recommended Application:
SIS 530/620 style chipset
Output Features:
• - 3 CPU @ 2.5V/3.3V up to 133.3 MHz.
• - 6 PCI @ 3.3V (including 1 free-running)
• - 13 SDRAMs @ 3.3V up to 133.3MHz.
• - 3 REF @ 3.3V, 14.318MHz
• - 1 clock @ 24/14.3 MHz selectable output for SIO
• - 1 Fixed clock at 48MHz (3.3V)
• - 1 IOAPIC @ 2.5V / 3.3V
Features:
• Up to 133MHz frequency support
• Support power management: CPU, PCI, SDRAM stop and
Power down Mode from I2C programming.
• Spread spectrum for EMI control ( ± 0.25% center spread
& 0 to -0.5% down spread).
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU – CPU<175ps
• SDRAM – SDRAM < 350ps
• CPU–SDRAM < 500ps
• CPU(early) – PCI : 1-4ns (typ. 2ns)
• PCI – PCI <500ps
Pin Configuration
VDDR/X
*MODE/REF0
GNDREF
X1
X2
VDDPCI
*FS1/PCICLK_F
*FS2.PCICLK0
GNDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
SDRAM12
GNDSDR
*CPU_STOP# /SDRAM11
*PCI_STOP# /SDRAM10
VDDSD/C
*SDRAM_STOP# /SDRAM9
*PD# /SDRAM8
GNDFIX
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDLAPIC
47 IOAPIC
46 REF1/SD_SEL#*
45 GNDLAPIC
44 REF2/CPU2.5_3.3#*
43 CPUCLK1
42 VDDLCPU
41 CPUCLK2
40 CPUCLK3
39 GNDCPU
38 SDRAM0
37 SDRAM1
36 VDDSDR
35 SDRAM2
34 SDRAM3
33 GNDSDR
32 SDRAM4
31 SDRAM5
30 VDDSDR
29 SDRAM6
28 SDRAM7
27 GNDSDR
26 48MHz/FS0*
25 SIO/SEL24_14#MHz*
48-Pin SSOP
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
Block Diagram
SEL24_14#
X1
X2
MODE
FS(2:0)
CPU3.3#_2.5
SD_SEL#
3
SDRAM_STOP#
CPU_STOP#
PCI_STOP#
PD#
SDATA
SCLK
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
LATCH
POR
5
Control
Logic
Config.
Reg.
/2
STOP
CPU_STOP
PCI
CLOCK
DIVDER
STOP
PCI_STOP
48MHz
SIO
3 REF(2:0)
IOAPIC
3 CPUCLK (3:1)
13 SDRAM (12:0)
5 PCICLK (4:0)
PCICLK_F
Functionality
SD_SEL FS2
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
CPU SDRAM
MHZ MHZ
0 90.00 90.00
1 66.70 100.05
0 95.00 63.33
1 100.00 66.66
0 100.00 75.00
1 112.00 74.66
0 124.00 82.66
1 97.00 97.00
0 66.70 66.70
1 75.00 75.00
0 83.30 83.30
1 95.00 95.00
0 100.00 100.00
1 112.00 112.00
0 124.00 124.00
1 133.30 133.30
PCI
MHZ
30.00
33.35
31.66
33.33
30.00
37.33
31.00
32.33
33.35
30.00
33.32
31.66
33.33
37.33
31.00
33.33
Note: REF, IOAPIC = 14.318MHz
9248-128 Rev B 11/16/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-128
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
-
PWD
1
1
1
1
1
1
1
X
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3
CPUCLK2
CPUCLK1
FS0#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
X
1
1
1
1
1
1
1
Description
FS1#
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
25
26
15
17
18
20
21
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
24/14MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
47
-
44
46
2
PWD
1
X
1
1
X
1
1
1
Description
(Reserved)
FS2#
(Reserved)
IOAPIC
SD_SEL#
REF2
REF1
REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-128
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-128. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-128.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-128.PDF ] | |
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