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PDF ICS9248-151 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-151 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-151
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
VIA Apollo Pro 266 style chipset.
Output Features:
• 3 - CPUs @ 2.5V, up to 200MHz.
• 3 - IOAPIC @ 2.5V, ½ PCI frequency
• 9 - PCI @ 3.3V,
• 1 - 48MHz, @ 3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 2 - REF @ 3.3V, 14.318MHz.
• 3 - AGP @ 3.3V
Features:
• Up to 200MHz frequency support
• Support power management: PCI, CPU stop
and Power Down.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU – CPU: <175ps
• PCI – PCI: <500ps
• CPU(early)-PCI: Min=1.0ns, Max=2.5ns
• CPU Cycle to cycle jitter: < 250ps
Pin Configuration
VDDREF
GND
X1
X2
AVDD48
*FS3/48MHz
*FS2/24_48MHz
GND
PCICLK_F
PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*FS1
*FS0
AGPCLK0
VDDAGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF0
47 REF1/FS4*
46 VDDLAPIC
45 IOAPIC0
44 IOAPIC1
43 GND
42 IOAPIC2
41 VDDLCPU
40 GND
39 CPUCLK0
38 CPUCLK1
37 VDDLCPU
36 GND
35 CPUCLK2/F
34 CPU_STOP#*
33 PCI_STOP#*
32 PD*
31 AVDD
30 GND
29 SDATA
28 SCLK
27 AGPCLK2
26 AGPCLK1
25 GND
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
Stop/F
AGP
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
Stop
Functionality
48MHz
24_48MHz
2 REF (1:0)
2 CPUCLK (1:0)
CPUCLK2/F
3 AGPCLK (2:0)
3 IOAPIC (2:0)
8 PCICLK (7:0)
PCICLK_F
FS4 FS3 FS2 FS1 FS0
00000
0000 1
000 10
000 11
00 100
00 10 1
00 110
00 111
0 1000
0 100 1
0 10 10
0 10 11
0 1100
0 110 1
0 1110
0 1111
CPU
(MHz)
200.00
190.00
180.00
170.00
166.00
160.00
150.00
145.00
140.00
136.00
130.00
124.00
66.67
100.00
118.00
133.33
AGP
(MHz)
80.00
76.00
72.00
68.00
66.40
64.00
75.00
72.50
70.00
68.00
65.00
62.00
66.67
66.67
78.67
66.67
PCICLK
(MHz)
40.00
38.00
36.00
34.00
33.20
32.00
37.50
36.25
35.00
34.00
32.50
31.00
33.34
33.33
39.33
33.34
9248-151 Rev B 01/29/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-151
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
35
-
-
-
35
38
39
42
PWD
DESCRIPTION
SEL_CPUF#;
0 0=CPUCLK2 will be free running
1=CPUCLK2 will not be free running
1 (Reserved)
X FS4#
X FS3#
1 CPUCLK2
1 CPUCLK1
1 CPUCLK0
1 IOAPIC2
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
-
X FS2#
Bit 6 -
0
SEL24_48
0=24MHz 1=48MHz
Bit 5
6
1 48MHz
Bit 4 7
1 24_48MHz
Bit 3
9
1 PCICLK_F
Bit 2 27
1 AGPCLK2
Bit 1 26
1 AGPCLK1
Bit 0 23
1 AGPCLK0
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
20
18
17
16
14
13
11
10
PWD
DESCRIPTION
1 PCICLK7
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
- 1 (Reserved)
- 1 (Reserved)
44 1 IOAPIC1
45 1 IOAPIC0
- 1 (Reserved)
- 1 (Reserved)
47 1 REF1
48 1 REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-151
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-151. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
IOAPIC
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-151.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-151
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-151.PDF ] | |
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