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PDF ICS9248-103 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-103 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9248 - 103
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9248-103 is the single chip clock solution for
Notebook designs using the 440BX or the VIAApollo Pro 133
style chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-103
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Block Diagram
Features
Up to 137MHz frequency support
Spread Spectrum for EMI control
Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum
Provides the following system clocks
- 4-CPUs @ 2.5/3.3V, up to 137MHz
(including CPUCLK_F)
- 9-SDRAMs @3.3V, up to 137MHz
(including SDRAM_F)
- 8-PCI @3.3V, CPU/2 or CPU/3
(including 3 free running PCICLK_Fs)
- 1-24/48MHz @3.3V
- 1-48MHz @3.3V fixed
- 2-REF @3.3V, 14.318MHz.
Efficient Power management scheme through PCI
and STOP CLOCKS
Spread Spectrum ± .25%, & 0 to -0.5% down spread
Pin Configuration
Power Groups
VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F
VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F
VDD48, GND48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
VDDCOR = PLL CORE
9248-103 Rev C 10/14/99
48-Pin SSOP
* Internal Pull-up Resistor of 120K to VDD
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
46
-
-
39
42
43
45
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
CPUCLK_F (Act/Inact)
(Reserved)
(Reserved)
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
7
18
17
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
PCICLK_F0 (Act/Inact)
PCICLK4(Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
PCICLK_F1 (Act/Inact)
PCICLK_F2 (Act/Inact)
ICS9248 - 103
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
28
29
31
32
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
5 Page 
ICS9248 - 103
Fig. 2a
Fig. 2b
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-103.PDF ] | |
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