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PDF M464S0924ETS Data sheet ( Hoja de datos )

Número de pieza M464S0924ETS
Descripción 64MB / 128MB Unbuffered SODIMM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! M464S0924ETS Hoja de datos, Descripción, Manual

64MB, 128MB Unbuffered SODIMM
SDRAM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based on 128Mb E-die
64-bit Non ECC
Revision 1.4
March. 2004
Rev. 1.4 March. 2004

1 page




M464S0924ETS pdf
64MB, 128MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
A0 ~ A11
Address
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11
Column address : (x16 : CA0 ~ CA8)
BA0 ~ BA1 Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
CAS
Row address strobe
Column address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
VDD/VSS
Data input/output
Power supply/ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Rev. 1.4 March. 2004

5 Page





M464S0924ETS arduino
64MB, 128MB Unbuffered SODIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
3.3V
Output
870
1200
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
SDRAM
Unit
V
V
ns
V
Z0 = 50
Vtt = 1.4V
50
50pF
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
(Fig. 2) AC output load circuit
Parameter
Symbol
Version
- 7A
Unit
Row active to row active delay
tRRD(min)
15
ns
RAS to CAS delay
tRCD(min)
20
ns
Row precharge time
tRP(min)
20
ns
Row active time
tRAS(min)
tRAS(max)
45
100
ns
us
Row cycle time
tRC(min)
65
ns
Last data in to row precharge
tRDL(min)
2
CLK
Last data in to Active delay
tDAL(min)
2 CLK + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
Last data in to burst stop
tBDL(min)
1
CLK
Col. address to col. address delay
tCCD(min)
1
CLK
Number of valid output data
CAS latency=3
CAS latency=2
2
ea
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note
1
1
1
1
1
2
2
2
3
4
Rev. 1.4 March. 2004

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