PDF M464S6453CKS Data sheet ( Hoja de datos )

Número de pieza	M464S6453CKS
Descripción	PC133/PC100 SODIMM
Fabricantes	Samsung semiconductor
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No Preview Available ! M464S6453CKS Revision History Revision 0.0 (Sept. 2001) Revision 0.1 (Feb. 2002) - Typo in SPD 127byte corrected PC133/PC100 SODIMM This is to advise Samsung customers that, until August 1, 2003, in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones, telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are, however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package Rev. 0.1 Feb. 2002 1 page M464S6453CKS PC133/PC100 SODIMM ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VD D supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VI N, VOUT VDD , VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 16 50 Unit V V °C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to V SS = 0V, TA = 0 to 70 °C) Parameter Symbol Min Typ Max Unit Supply voltage VD D 3.0 3.3 3.6 V Input high voltage Input low voltage Output high voltage Output low voltage VI H 2.0 3.0 VDDQ+0.3 V VIL -0.3 0 0.8 V VO H 2.4 - - V VOL - - 0.4 V Input leakage current ILI -10 - 10 uA Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. Note 1 2 IOH = -2mA IOL = 2mA 3 CAPACITANCE (VDD = 3.3V, T A = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Symbol Min Input capacitance (A0 ~ A12, BA0 ~ BA1) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK1) Input capacitance (CS0 ~ CS1) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63) CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT 45 45 35 25 35 10 15 Max 90 90 60 45 60 25 30 Unit pF pF pF pF pF pF pF Rev. 0.1 Feb. 2002 5 Page M464S6453CKS PC133/PC100 SODIMM M464S6453CKS-L7A/L1H/L1L, C7A/C1H/C1L(Intel SPD 1.2B ver. based) •Organization : 64MX64 •Composition : 64MX8 *8 •Used component part # : K4S510832C-L7A/C7A/L1H/C1H/L1L/C1L •# of rows in module : 2 rows •# of banks in component : 4 banks •Feature : 1,200 mil height & double sided •Refresh : 8K/64ms •Contents : Byte # Function described 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 7 ...... Data width of this assembly 8 Voltage interface standard of this assembly 9 SDRAM cycle time from clock @CAS latency of 3 10 SDRAM access time from clock @CAS latency of 3 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes Function Supported -7A -1H -1L 128bytes 256bytes (2K-bit) SDRAM 13 10 2 Rows 64 bits - LVTTL 7.5ns 10ns 10ns 5.4ns 6ns 6ns Non parity 7.8us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Non-buffered/Non-Regis- tered & redundant addressing 22 SDRAM device attributes : General 23 SDRAM cycle time @CAS latency of 2 24 SDRAM access time @CAS latency of 2 25 SDRAM cycle time @CAS latency of 1 26 SDRAM access time @CAS latency of 1 27 Minimum row precharge time (=tRP ) 28 Minimum row active to row active delay (t RRD) 29 Minimum RAS to CAS delay (=tRCD ) 30 Minimum activate precharge time (=tRAS) 31 Module Row density 32 Command and Address signal input setup time 33 Command and Address signal input hold time 34 Data signal input setup time +/- 10% voltage toleance, Burst Read Single bit Write precharge all, auto precharge 10ns 10ns 12ns 6ns 6ns 7ns - - 20ns 15ns 20ns 20ns 20ns 45ns 50ns 50ns 2 Rows of 256MB 1.5ns 2ns 2ns 0.8ns 1ns 1ns 1.5ns 2ns 2ns Hex value -7A -1H -1L 80h 08h 04h 0Dh 0Ah 02h 40h 00h 01h 75h A0h A0h 54h 60h 60h 00h 82h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h A0h C0h 60h 60h 70h 00h 00h 14h 0Fh 14h 14h 14h 2Dh 32ns 32ns 40h 15h 20h 20h 08h 10h 10h 15h 20h 20h Note 1 1 2 2 2 2 2 2 Rev. 0.1 Feb. 2002 11 Page

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