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PDF SCD1284 Data sheet ( Hoja de datos )
| Número de pieza | SCD1284 | |
| Descripción | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports | |
| Fabricantes | Intel | |
| Logotipo |  |
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CD1284
IEEE 1284-Compatible Parallel Interface Controller
with Two High-Speed Asynchronous Serial Ports
Product Features
Datasheet
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol
parallel port:
s Hardware implementation of all modes of
the IEEE STD (Standard) 1284
specification (including automatic
negotiation)
— Centronics-compatible mode
— Reverse Byte mode
— Reverse Nibble mode
— ECP (extended capabilities port) mode
with run-length encoding/decoding
— EPP (enhanced parallel port) mode
— Up to 2-Mbytes/sec. transfer rate in ECP
and EPP modes
s 64-byte parallel FIFO with DMA interface
Two Serial UARTs
s Serial channel asynchronous protocol
support to 115.2 kbps (register-set-
compatible and functionally identical to
CD1400)
— Twelve-byte FIFOs for each transmitter
and receiver with programmable
threshold for receive FIFO interrupt
generation
— Improved interrupt schemes: Good
Data interrupts eliminate the need for
character status check
— User-programmable and automatic flow
control for serial channels
— Special character recognition and
generation.
— Special character processing,
particularly useful for UNIX
environments, optionally handled
automatically by the serial channels.
— Six modem control signals per channel
(DTR, DSR, RTS, CTS, CD, and RI)
As of May 2001, this document replaces the Basis
Communications Corp. document.
CL-CD1284 — IEEE 1284-Compatible Parallel Interface Controller
May 2001
1 page  
IEEE 1284-Compatible Parallel Interface Controller — CD1284
6.5.2 Hardware-Activated Service Examples ................................................102
6.6 Baud Rate Derivation ........................................................................................102
6.7 Baud Rate Tables..............................................................................................103
6.8 ASCII Code Tables............................................................................................106
6.8.1 Hexadecimal — Character ...................................................................106
6.8.2 Decimal — Character ...........................................................................107
7.0 Detailed Register Descriptions.........................................................................108
7.1 Global Registers................................................................................................108
7.1.1 Channel Access Register .....................................................................108
7.1.2 Global Firmware Revision Code Register ............................................108
7.1.3 General-Purpose I/O Direction Register...............................................109
7.1.4 General-Purpose I/O Register..............................................................109
7.1.5 Modem Interrupting Channel Register .................................................109
7.1.6 Modem Interrupt Register.....................................................................110
7.1.7 Parallel Interrupt Register.....................................................................111
7.1.8 Prescaler Period Register ....................................................................111
7.1.9 Receive Interrupting Channel Register ................................................112
7.1.10 Receive Interrupt Register....................................................................112
7.1.11 Service Request Register.....................................................................112
7.1.12 Transmit Interrupting Channel Register ...............................................113
7.1.13 Transmit Interrupt Register...................................................................113
7.2 Virtual Registers ................................................................................................113
7.2.1 Modem Interrupt Status Register .........................................................114
7.2.2 Modem Interrupt Vector Register .........................................................114
7.2.3 Parallel Interrupt Vector Register .........................................................115
7.2.4 Receive Data/Status Registers ............................................................115
7.2.5 Receive Interrupt Vector Register ........................................................116
7.2.6 Transmit Data Register ........................................................................117
7.2.7 Transmit Interrupt Vector Register .......................................................117
7.2.8 End of Service Request Register .........................................................118
7.3 Channel Registers.............................................................................................118
7.3.1 Channel Command Register ................................................................118
7.3.2 Channel Control Status Register..........................................................122
7.4 Channel Registers — Parallel Pipeline .............................................................123
7.4.1 Channel Option Register 1 ...................................................................123
7.4.2 Channel Option Register 2 ...................................................................124
7.4.3 Channel Option Register 3 ...................................................................125
7.4.4 Channel Option Register 4 ...................................................................126
7.4.5 Channel Option Register 5 ...................................................................128
7.4.6 Local Interrupt Vector Register.............................................................128
7.4.7 LNext Character Register.....................................................................129
7.5 Modem Change Option Registers .....................................................................129
7.5.1 Modem Change Option Register 1.......................................................129
7.5.2 Modem Change Option Register 2.......................................................130
7.5.3 Modem Signal Value Register 1...........................................................130
7.5.4 Modem Signal Value Register 2...........................................................131
7.5.5 Receive Baud Rate Period Register.....................................................131
7.5.6 Receive Clock Option Register ............................................................131
7.5.7 Received Data Count Register .............................................................132
Datasheet
5
5 Page 
IEEE 1284-Compatible Parallel Interface Controller — CD1284
Figure 1. Functional Block Diagram
DMA
CONTROL
Compression/
Decompression
DATA Mover
DATA PIPELINE
64 Bytes
FIFO
MPU
REGISTERS
AND FIFO
RAM
MODIFIED CD1400 CORE
GENERAL-
PURPOSE I/
O PORT
Control
State
Machine
Level-2
Electrical
Interface
IEEE1284 PERIPHERAL
PARALLEL PORT
SERIAL
PORT #1
SERIAL
PORT #2
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SCD1284.PDF ] | |
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