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PDF CA3306 Data sheet ( Hoja de datos )

Número de pieza CA3306
Descripción 6-Bit / 15 MSPS / Flash A/D Converters
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CA3306 Hoja de datos, Descripción, Manual

August 1997
CA3306, CA3306A,
CA3306C
6-Bit, 15 MSPS,
Flash A/D Converters
Features
Description
• CMOS Low Power with Video Speed (Typ) . . . . .70mW
• Parallel Conversion Technique
• Signal Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• 15MHz Sampling Rate with Single 5V Supply
• 6-Bit Latched Three-State Output with Overflow Bit
• Pin-for-Pin Retrofit for the CA3300
Applications
• TV Video Digitizing
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• High Speed Oscilloscope Storage/Display
• General Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
The CA3306 family are CMOS parallel (FLASH) analog-to-digital
converters designed for applications demanding both low power
consumption and high speed digitization. Digitizing at 15MHz, for
example, requires only about 50mW.
The CA3306 family operates over a wide, full scale signal input volt-
age range of 1V up to the supply voltage. Power consumption is as
low as 15mW, depending upon the clock frequency selected. The
CA3306 types may be directly retrofitted into CA3300 sockets, offer-
ing improved linearity at a lower reference voltage and high operat-
ing speed with a 5V supply.
The intrinsic high conversion rate makes the CA3306 types ideally
suited for digitizing high speed signals. The overflow bit makes pos-
sible the connection of two or more CA3306s in series to increase
the resolution of the conversion system. A series connection of two
CA3306s may be used to produce a 7-bit high speed converter.
Operation of two CA3306s in parallel doubles the conversion speed
(i.e., increases the sampling rate from 15MHz to 30MHz).
Sixty-four paralleled auto balanced comparators measure the input
voltage with respect to a known reference to produce the parallel bit
outputs in the CA3306. Sixty-three comparators are required to
quantize all input voltage levels in this 6-bit converter, and the addi-
tional comparator is required for the overflow bit.
Ordering Information
PART NUMBER LINEARITY (INL, DNL)
CA3306E
±0.5 LSB
CA3306CE
±0.5 LSB
CA3306M
±0.5 LSB
CA3306CM
±0.5 LSB
CA3306D
±0.5 LSB
CA3306CD
±0.5 LSB
CA3306J3
±0.5 LSB
CA3306J3
±0.5 LSB
Pinouts
CA3306 (PDIP, SBDIP)
TOP VIEW
SAMPLING RATE
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
TEMP. RANGE (oC)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
18 Ld PDIP
18 Ld PDIP
20 Ld SOIC
20 Ld SOIC
18 Ld SBDIP
18 Ld SBDIP
20 Ld CLCC
20 Ld CLCC
PKG. NO.
E18.3
E18.3
M20.3
M20.3
D18.3
D18.3
J20.B
J20.B
CA3306 (SOIC)
TOP VIEW
CA3306 (CLCC)
TOP VIEW
(MSB) B6 1
OVERFLOW 2
VSS 3
VZ 4
CE2 5
CE2 6
CLK 7
PHASE 8
VREF+ 9
18 B5
17 B4
16
REF
CENTER
15 B3
14 B2
13 B1 (LSB)
12 VDD
11 VIN
10 VREF-
(MSB) B6 1
OVERFLOW 2
VSS 3
NC 4
VZ 5
CE2 6
CE1 7
CLK 8
PHASE 9
VREF+ 10
20 B5
19 B4
18
REF
CENTER
17 B3
16 B2
15 B1 (LSB)
14 VDD
13 NC
12 VIN
11 VREF-
3 2 1 20 19
VSS 4
VZ 5
18
REF
CENTER
17 B3
NC 6
16 B2
CE2 7
15 B1 (LSB)
CE1 8
14 VDD
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-8
File Number 3102.1

1 page




CA3306 pdf
CA3306, CA3306A, CA3306C
Timing Waveforms
COMPARATOR DATA IS LATCHED
DECODED DATA IS SHIFTED TO OUTPUT REGISTERS
CLOCK IF
PHASE IS HIGH
φ2 φ1 φ2 φ1 φ2
CLOCK IF
PHASE IS LOW
DATA
N-2
AUTO
BALANCE
SAMPLE
N+1
tD
tH
AUTO
BALANCE
SAMPLE
N+2
DATA
N-1
DATA
N
FIGURE 1. INPUT-TO-OUTPUT
CE1
CE2
tDIS
tEN
BITS 1-6
DATA
HIGH
IMPEDANCE
tDIS
DATA
tDIS
HIGH
IMPEDANCE
DATA
OF DATA
HIGH
IMPEDANCE
DATA
FIGURE 2. OUTPUT ENABLE
SAMPLE ENDS
CLOCK
φ2
φ1
tD
OUTPUT
OLD DATA
FIGURE 3A.
CLOCK
φ2
SAMPLE ENDS
φ2
CLOCK φ 1
φ2
φ1 φ2
NEW DATA OUTPUT
OLD
DATA
tD
OLD
DATA +1
SAMPLE ENDS
φ1 φ2
φ1
FIGURE 3B.
φ2
OUTPUT
tD
OLD DATA
INVALID
DATA
FIGURE 3C.
FIGURE 3. PULSE MODE
NEW
DATA
φ1
NEW
DATA
4-12

5 Page





CA3306 arduino
CA3306, CA3306A, CA3306C
The CA3306 outputs a short (less than 10ns) current spike
of up to several mA amplitude (See Typical Performance
Curves) at the beginning of the sample phase. (To a lesser
extent, a spike also appears at the beginning of auto bal-
ance.) The driving source must recover from the spike by the
end of the same phase, or a loss of accuracy will result.
A locally terminated 50or 75source is generally suffi-
cient to drive the CA3306. If gain is required, a high speed,
fast settling operational amplifier, such as the HA-5033,
HA-2542, or HA5020 is recommended.
Digital Input And Output Interfacing
The two chip-enable and the phase-control inputs are stan-
dard CMOS units. They should be driven from less than 0.3
x VDD to at least 0.7 x VDD. This can be done from 74HC
series CMOS (QMOS), TTL with pull-up resistors, or, if VDD
is greater than the logic supply, open collector or open drain
drivers plus pull-ups. (See Figure 20.)
The clock input is more critical to timing variations, such as
φ1 becoming too short, for instance. Pull-up resistors should
generally be avoided in favor of active drivers. The clock
input may be capacitively coupled, as it has an internal 50k
feedback resistor on the first buffer stage, and will seek its
own trip point. A clock source of at least 1VP-P is adequate,
but extremely non-symmetrical waveforms should be
avoided.
The output drivers have full rail-to-rail capability. If driving
CMOS systems with VDD below the VDD of the CA3306, a
CD74HC4050 or CD74HC4049 should be used to step down
the voltage. If driving LSTTL systems, no step-down should
be necessary, as most LSTTLs will take input swings up to
10V to 15V.
Although the output drivers are capable of handling typical
data bus loading, the capacitor charging currents will pro-
duce local ground disturbances. For this reason, an external
bus driver is recommended.
If VIN for the first transition is greater than the theoretical,
then the 50pot should be connected between VREF and a
negative voltage of about 2 LSBs. The trim procedure is as
stated previously.
Gain Trim
In general the gain trim can also be done in the preamp
circuitry by introducing a gain adjustment for the operational
amplifier. When this is not possible, then a gain adjustment
circuit should be made to adjust the reference voltage. To
tprearnfosirtmiont.hiTshtartimv,olVtalNgesihso1u/l2d
be set to
LSB less
the
than
63 to overflow
VREF+ and is
calculated as follows:
VlN (63 to 64 transition) = VREF - VREF/128
= VREF(127/128).
To perform the gain trim, first do the offset trim and then
apply the required VlN for the 63 to overtlow transition. Now
adjust VREF+ until that transition occurs on the outputs.
Midpoint Trim
The reference center (RC) is available to the user as the
midpoint of the resistor ladder. To trim the midpoint, the
offset and gain trims should be done first. The theoretical
transition from count 31 to 32 occurs at 311/2 LSBs. That
voltage is as follows:
VlN (31 to 32 transition) = 31.5 (VREF/64)
= VREF(63/128).
An adjustable voltage follower can be connected to the RC
pin or a 2K pot can be connected between VREF+ and
VREF- with the wiper connected to RC. Set VlN to the 31 to
32 transition voltage, then adjust the voltage follower or the
pot until the transition occurs on the output bits.
The Reference Center point can also be used to create
unique transfer functions. The user must remember, however,
that there is approximately 120in series with the RC pin.
Increased Accuracy
In most cases the accuracy of the CA3306 should be
sufficient without any adjustments. In applications where
accuracy is of utmost importance, three adjustments can be
made to obtain better accuracy; i.e., offset trim, gain trim,
and midpoint trim.
Offset Trim
In general offset correction can be done in the preamp
circuitry by introducing a DC shift to VlN or by the offset trim
of the operational amplifier. When this is not possible the
VREF- input can
theoretical input
be adjusted to produce an
voltage to produce the first
offset trim. The
transition is 1/2
LSB. The equation is as follows:
VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64)
= VREF/128.
If VlN for the first transition is less than the theoretical, then a
saicncgolem-tpulirsnh5t0he apdojut sctomnennetc.teSdetbVeltNwetoen1/2VRLSEFB-
and
and
ground
trim the
will
pot
until the 0 to 1 transition occurs.
Applications
7-Bit Resolution
To obtain 7-bit resolution, two CA3306s can be wired
together. Necessary ingredients include an open-ended lad-
der network, an overtlow indicator, three-state outputs, and
chip-enabler controls - all of which are available on the
CA3306.
The first step for connecting a 7-bit circuit is to totem-pole
the ladder networks, as illustrated in Figure 17. Since the
absolute resistance value of each ladder may vary, external
trim of the mid-reference voltage may be required.
The overflow output of the lower device now becomes the
seventh bit. When it goes high, all counts must come from
the upper device. When it goes low, all counts must come
from the lower device. This is done simply by connecting the
lower overflow signal to the CE1 control of the lower A/D
converter and the CE2 control of the upper A/D converter.
The three-state outputs of the two devices (bits 1 through 6)
are now connected in parallel to complete the circuitry.
4-18

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