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PDF CA3304 Data sheet ( Hoja de datos )
| Número de pieza | CA3304 | |
| Descripción | 4-Bit / 25 MSPS / Flash A/D Converters | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CA3304, CA3304A
August 1997
4-Bit, 25 MSPS,
Flash A/D Converters
Features
• CMOS/SOS Low Power with Video Speed (Typ) . . 25mW
• Parallel Conversion Technique
• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• 25MHz Sampling Rate (40ns Conversion Time) at 5V
Supply
• 4-Bit Latched Three-State Output with Overflow and
Data Change Outputs
• 1/8 LSB Maximum Nonlinearity (A Version)
• Inherent Resistance to Latch-Up Due to SOS Process
• Bipolar Input Range with Optional Second Supply
• Wide Input Bandwidth (Typ) . . . . . . . . . . . . . . . . 25MHz
Applications
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
• RSSI Circuits
Description
The Intersil CA3304 is a CMOS parallel (FLASH) analog-to-
digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz-
ing at 25MHz, for example, requires only about 35mW.
The CA3304 operates over a wide, full-scale signal input
voltage range of 0.5V up to the supply voltage. Power
consumption is as low as 10mW, depending upon the clock
frequency selected.
The intrinsic high conversion rate makes the CA3304 types
ideally suited for digitizing high speed signals. The overflow
bit makes possible the connection of two or more CA3304s
in series to increase the resolution of the conversion system.
A series connection of two CA3304s may be used to pro-
duce a 5-bit, 25MHz converter. Operation of two CA3304s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 25MHz to 50MHz). A data change pin
indicates when the present output differs from the previous,
thus allowing compaction of data storage.
Sixteen paralleled auto-balanced voltage comparators mea-
sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the CA3304. Fifteen com-
parators are required to quantize all input voltage levels in this
4-bit converter, and the additional comparator is required for
the overflow bit.
Ordering Information
PART NUMBER LINEARITY (INL, DNL)
CA3304E
±0.25 LSB
CA3304AE
±0.125 LSB
CA3304M
±0.25 LSB
CA3304AM
±0.125 LSB
CA3304D
±0.25 LSB
CA3304AD
±0.125 LSB
Pinout
SAMPLING RATE
25MHz (40ns)
25MHz (40ns)
25MHz (40ns)
25MHZ (40ns)
25MHz (40ns)
25MHz (40ns)
TEMP. RANGE (oC)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC (W)
16 Ld SOIC (W)
16 Ld SBDIP
16 Ld SBDIP
CA3304 (SBDIP, PDIP, SOIC)
TOP VIEW
PKG. NO.
E16.3
E16.3
M16.3
M16.3
D16.3
D16.3
BIT 1 (LSB) 1
BIT 2 2
BIT 3 3
BIT 4 4
DATA CHANGE (DC) 5
OVERFLOW (OF) 6
CE2 7
VSS 8
16 VDD
15 CLK
14 VAA-
13 VREF-
12 VREF+
11 VIN
10 VAA+
9 CE1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-7
File Number 1790.2
1 page  
CA3304, CA3304A
Functional Diagram
VIN
11
1/2R
12
VREF +
R
φ2 φ1
φ1 φ1 φ1
VAA+
10
VDD
16
†CAB #16
COUNT
16
DQ
LATCH
16
φ2 OUTPUT
REGISTER
DQ
CLK
DQ
CLK
THREE-STATE
DRIVERS
5
DATA
CHANGE
6 OVERFLOW
DQ
CLK
R
D
COUNT
8
Q
ENCODER
LOGIC
†CAB #8
LATCH
8
ARRAY
DQ
CLK
R
DQ
CLK
4 BIT 4
3 BIT 3
2 BIT 2
R
VREF- 1/2R
13
50kΩ
†CAB COMPARATOR #1
COUNT
1
DQ
LATCH
0
DQ
CLK
1 BIT 1 (LSB)
CLOCK
15
φ1 (AUTO BALANCE)
φ2 (SAMPLE UNKNOWN)
†Cascaded Auto Balance (CAB)
14
VAA-
8
VSS
9 CE1
7 CE2
NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to VDD and VSS. Analog inputs and clock have
standard CMOS protection networks to VAA+ and VAA-.
Timing Diagrams
DATA SHIFTED INTO
OUTPUT REGISTERS
1
CLOCK
0
1
B1 - B4, DC & OF
0
φ1
AUTO
BALANCE
tHO
φ2
SAMPLE 1
COMPARATOR DATA
LATCHED
AUTO
BALANCE
SAMPLE 2
AUTO
BALANCE
SAMPLE 3
DATA VALID 0
DATA VALID 1
DATA VALID 2
tD
FIGURE 1. TIMING DIAGRAM
CE1
CE2
BITS 1-4
DC, OF
tDIS
tEN
HIGH
IMPEDANCE
tDIS
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING
tEN
HIGH
IMPEDANCE
HIGH
IMPEDANCE
4-11
5 Page 
CA3304, CA3304A
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + VCORR)/6.02,
where: VCORR = 0.5dB.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input signal.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended han-
dling practices for CMOS devices are described in
lCAN-6525. “Guide to Better Handling and Operation of
CMOS Integrated Circuits.”
OPERATING
Operating Voltage
During operation near the maximum supply voltage limit, care
should be taken to avoid or suppress power supply turn-on
and turn-off transients, power supply ripple, or ground noise;
any of these conditions must not cause the power supply
voltages to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input signals
should never be greater than VDD or VAA+ nor less than VSS
or VAA- (depending upon which supply the protection network
is referenced. See Maximum Ratings.). Input currents must
not exceed 20mA even when the power supply is off.
Unused Inputs
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VDD or
VSS, whichever is appropriate.
Output Short Circuits
Shorting of outputs to any supply potential may damage
CMOS devices by exceeding the maximum device dissipation.
+FULL
SCALE
REF.
+5V
BUFFER
INPUT
1K
ADJUST
CENTER
+5V
VAA+ DC
VDD
OF
VREF+ B4
VIN B3
VREF- B2
VAA- B1
VSS CE1
CLK CE2
CA3304
NC
NC
CLK
VAA+
VDD
VREF +
VIN
VREF -
VAA-
VSS
DC
OF
B4
B3
B2
B1
CE1
CE2
NC
+5V
CA3304
CLOCK
INPUT
B5 MSB
B4
B3
B2
B1
FIGURE 13. TYPICAL CA3304 5-BIT CONFIGURATION
OVERFLOW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14V15 V16
INPUT VOLTAGE
FIGURE 14. IDEAL TRANSFER CURVE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-17
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CA3304.PDF ] | |
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