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PDF TC9204M Data sheet ( Hoja de datos )
| Número de pieza | TC9204M | |
| Descripción | 4-Port 10/100/1000 Smart Ethernet Switch | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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TC9204M
Preliminary Data Sheet
4-Port 10/100/1000 Smart Ethernet Switch
Features
Stand Alone Switch On A Chip
4 Ethernet 10/100/1000 ports
MII/GMII interface for all ports
Four Classes of Service (CoS) selectable for
each port and/or checked via IP Header and
802.1Q VLAN Tag
Support 4 port-based VLANs
Maximum throughput (wire speed), non
head-of-line blocking architecture
Embedded SSRAM for packet buffer /
address table, no external memory required
8K MAC address table
25 MHz crystal input only
Each port is configurable to 10 full/half duplex,
100 full/half duplex and 1000 full duplex mode
Flow-control ability is able to set for both full
and half duplex mode
Broadcast throttling
Port Mirroring
Serial EEPROM Interface, EEPROM is optional
MDIO master for PHY configuration / polling
0.18 micron technology
2.0V and 3.3V dual voltage power supply
Packaged in PQFP 208
General Description
TC9204M is a fully integrated 4-Port 10/100/1000
smart Ethernet switch controller designed for low
cost and high performance solutions. The chip
embeds necessary SSRAM for packet buffering
and MAC address table. It provides MII / GMII
interface for all ports.
A store-and-forward switching method using a
non-blocking architecture is implemented within
TC9204M to improve the availability and
bandwidth. The chip embeds SSRAM packet
buffer, which it supports normal and priority
queues for each transmission port.
TC9204M provides evolved CoS with four levels
of priority. The priority can be checked via layer 2
(802.1Q VLAN Tagging) and/or layer 3 (IP Header
TOS bits) packets. Port based priority is also
provided to ensure transmission with precedence
for all packets incoming from selected port(s).
This feature allows improved support for
multimedia applications.
The chip embeds IEEE 802.3 MAC functions for
each port and these functions support full and half
duplex modes for both 10 and 100 Mbits/s data
rates and full duplex for 1000 Mbit/s. Each port
includes dedicated receive and transmit FIFOs
with necessary logic to implement flow control for
both full and half duplex modes. TC9204M uses
IEEE 802.3x frame based flow control for full
duplex and backpressure for half duplex.
TC9204M handles an 8K address-lookup table
with searching, self-learning, and automatic aging
at very high speed and excellent address space
coverage. Forwarding rules are implemented
according to IEEE 802.1D specifications. Filtering
capabilities for bad packets and packets with
Reserved Group Address DA are also provided.
A port mirror feature, optionally including bad frames,
can be used for debugging network problems.
The pin configuration interface comprises 40
configurations, which are shared with GMII output
pins by latching the configuration data during
reset. An external EEPROM device can also be
used to configure the TC9204M at power-up. With
reference to pin configuration interface, the
EEPROM extends the chip’s configuration
capability with new features and enables a
jumper-less configuration mode using a parallel
interface for reprogramming. A virtual internal
EEPROM mode is also provided to enable the
use of the programming interface in the absence
of external EEPROM. TC9204M can make
effective use by most of its features using only the
pin configuration interface.
TC9204M includes a physical layer configuration /
polling entity, which it is use to configure the phy
functions and to monitor the physical layer
transceiver’s speed, duplex mode, link status and
full duplex flow control ability for each port. The
chip provides four modes for phy configurations,
which these modes include auto-negotiation
disable procedure for 10/100 speed modes. The
phy configuration information is stored in
EEPROM setting.
Confidential.
Copyright © 2003, IC Plus Corp.
1/49
July 29, 2003
TC9204M-DS-R05
1 page  
Pins Placement
TC9204M
Preliminary Data Sheet
NC
NC
NC
NC
Vdd 3.3
txd67
txd66
txd65
Vss 3.3
txd64
txd63
txd62
Vdd 3.3
txd61/priclass61
txd60/priclass60
txen6
gtxclk6
Vss 3.3
txer6
txclk6
crs6
col6
rxer6
Vdd 2.0
rxclk6
rxdv6
rxd60
rxd61
rxd62
Vss 2.0
rxd63
rxd64
rxd65
rxd66
rxd67
Vdd 3.3
Vss 3.3
Vdd 2.0
Vss 2.0
Vdd 3.3
Gnd
Vss 3.3
Gnd
Vdd 3.3
Vss 3.3
NC
NC
NC
NC
NC
NC
NC
208207206205204203202201200199198197196195194193192191190189188187186185184183182181180179178177176175174173172171170169168167166165164163162161160159158 157
1 156
2 155
3 154
4 153
5 152
6 151
7 150
8 149
9 148
10 147
11 146
12 145
13 144
14 143
15 142
16 141
17 140
18 139
19 138
20 137
21 136
22 135
23 134
24 133
TC9204M25 132
26 131
27 130
28 129
29 128
30 127
31 126
32 125
33 124
34 123
35 122
36 121
37 120
38 119
39 118
40 117
41 116
42 115
43 114
44 113
45 112
46 111
47 110
48 109
49 108
50 107
51 106
52 105
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100101102103104
NC
NC
NC
NC
NC
Gnd
Vdd 2.0
Gnd
Vss 3.3
VLANPrMap0
Vdd 3.3
VLANPrMAp1
EnVLANPr
IPTosMap0
IPTosMap1
EnlPPr
rxd27
rxd26
rxd25
rxd24
rxd23
Vss 3.3
rxd22
rxd21
rxd20
rxdv2
rxclk2
Vdd 3.3
rxer2
col2
crs2
txclk2
txer2
Vss 2.0
gtxclk2
txen2
txd20/priclass20
txd21/priclass21
txd22/PriBndw0
Vdd 2.0
txd23/PriBndw1
txd24
txd25
txd26
txd27
reset
SysCk
Vss 2.0
OvUnLED
BcstLED
Vdd 2.0
Gtxck
Confidential.
Copyright © 2003, IC Plus Corp.
5/49
July 29, 2003
TC9204M-DS-R05
5 Page 
TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No. Pin label
147 VLANPrMap0
148 Vss 3.3
149 Gnd
150 Vdd 2.0
151 Gnd
152 NC
153 NC
154 NC
155 NC
156 NC
157 Txd47
BcstThrot
158 Txd46
159 Txd45
FcBcstMode
160 Txd44
FcBcstEn
161 Txd43
162 Vss 2.0
163 Txd42
164 Txd41
Priclass41
Type
I/Opu
G
I
P
I
NA
NA
NA
NA
NA
I/Opd
I/Opd
I/Opd
I/Opd
I/Opd
G
I/Opd
I/Opd
Description
VLAN priority mapping
This configuration chooses between 4 hard-wired mapping schemes
for the associations of VLAN priority within the received packet and
one of the 4 priority levels set by PriClass. The resolution function is
used for the final priority class if the receiving port already has a
priority level assigned by PriClass configuration, or the VLAN
prioritization is active.
VLANPrMap(0)is latched on reset.
Digital ground for I/O
Digital +2.0V power supply for core
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
GMII transmit data - bit 7
Enables broadcast throttling.
'1' – Enable
'0' – Disable
BcstThrot is latched on reset.
GMII transmit data - bit 6
GMII transmit data - bit 5
This pin changes the flow control threshold’s behaviour if pin 160 is
set to logic 1 (It enables broadcast function).
'1' – only the flow control threshold on the broadcast queue is considered
'0' – flow control thresholds associated to each source port originating the
broadcast frames are considered FCBcstMode is latched on reset.
GMII transmit data - bit 4
Enables/disables flow control for broadcast packets.
'1' – enabled
'0' – disabled
FcBcstEn is latched on reset.
GMII/MII transmit data - bit 3
Digital ground for core
GMII/MII transmit data - bit 2
GMII/MII transmit data - bit 1
Priority class - most significant bit.
PriClass[4] is latched on reset.
Confidential.
Copyright © 2003, IC Plus Corp.
11/49
July 29, 2003
TC9204M-DS-R05
11 Page | ||
| Páginas | Total 49 Páginas | |
| PDF Descargar | [ Datasheet TC9204M.PDF ] | |
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