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PDF TC9208M Data sheet ( Hoja de datos )

Número de pieza TC9208M
Descripción 8-Port 10/100/1000 Smart Ethernet Switch
Fabricantes IC Plus 
Logotipo IC Plus Logotipo



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TC9208M
Preliminary Data Sheet
8-Port 10/100/1000 Smart Ethernet Switch
Features
Stand Alone Switch On A Chip
8 Ethernet 10/100/1000 ports
MII/GMII interface for all ports
Trunk group support
Four Classes of Service (CoS) selectable for
each port and/or checked via IP Header and
802.1Q VLAN Tag
Eight port-based VLANs
Maximum throughput, non head-of-line
blocking architecture
Embedded SSRAM packet buffer/address table
8K MAC address table
Each port is configurable to 10 full/half duplex,
100 full/half duplex and 1000 full duplex mode
Flow-control ability is able to set for both full
and half duplex mode
Broadcast throttling
Port Mirroring
Serial EEPROM Interface, EEPROM is optional
MDIO master for PHY configuration / polling
0.18 micron technology
2V and 3.3V dual voltage power supply
Packaged in PBGA 292
27 MHz crystal input only
General Description
TC9208M is a fully integrated 8 port 10/100/1000
smart Ethernet switch controller designed for low
cost and high performance solutions. The chip
embeds necessary SSRAM for packet buffering
and MAC address table. It provides MII / GMII
interface for all ports.
A store-and-forward switching method using a
non-blocking architecture is implemented within
TC9208M to improve the availability and
bandwidth. The chip embeds packet buffer, which
it supports normal and priority queues for each
transmission port.
TC9208M provides evolved CoS with four levels
of priority. The priority can be checked via layer 2
(802.1Q VLAN Tagging) and/or layer 3 (IP Header
TOS bits) packets. Port based priority is also
provided to ensure transmission with precedence
for all packets incoming from selected port(s).
This feature allows improved support for
multimedia applications.
The chip embeds IEEE 802.3 MAC functions for
each port and these functions support full and half
duplex modes for both 10 and 100 Mbits/s data
rates and full duplex for 1000 Mbit/s. Each port
includes dedicated receive and transmit FIFOs
with necessary logic to implement flow control for
both full and half duplex modes. TC9208M uses
IEEE 802.3x frame based flow control for full
duplex and backpressure for half duplex.
TC9208M handles an 8K address-lookup table
with searching, self-learning, and automatic aging,
at very high speed and excellent address space
coverage. Forwarding rules are implemented
according to IEEE 802.1D specifications. Filtering
capabilities for bad packets and packets with
Reserved Group Address DA are also provided.
Increased interconnection bandwidth can be
achieved by using TC9208M’s trunking
capabilities. Several load-balancing schemes are
provided through pin and EEPROM configuration.
A port mirror feature, which it includes bad frames
optionally, can be used for debugging network
problems.
The pin configuration interface comprises 40
configurations, which are shared with GMII output
pins by latching the configuration data during
reset. An external EEPROM device can also be
used to configure the TC9208M at power-up. With
reference to pin configuration interface, the
EEPROM extends the chip’s configuration
capability with new features and enables a
jumper-less configuration mode using a parallel
interface for reprogramming. A virtual internal
EEPROM mode is also provided to enable the
use of the programming interface in the absence
of external EEPROM. TC9208M can make
effective use by most of its features using only the
pin configuration interface.
TC9208M includes a physical layer configuration /
polling entity, which it is use to configure the phy
functions and to monitor the physical layer
transceiver’s speed, duplex mode, link status and
full duplex flow control ability for each port. The
chip provides four modes for phy configurations,
Confidential.
Copyright © 2003, IC Plus Corp.
1/53
August 1, 2003
TC9208M-DS-R06

1 page




TC9208M pdf
TC9208M
Preliminary Data Sheet
Pins Placement
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A RXD00
CRS0
COL0
TXD76
TXD73
TXD70
RXDV7 RXER7
RXD74
RXD73
RXD70
TXER6
TXD66
TXD63
TXD60
RXER6
RXD65
RXD64
RXD63
ARXD62
B
RXD03
RXD02
RXD01
TXD77
TXD74
TXD71 GTXCLK7 RXCLK7 RXD75
RXD72
CRS7
TXEN6 TXD65
TXD62 TXCLK6 RXCLK6 RXD66 RXD61 RXD60
BCRS6
C
RXD06
RXD05
RXD04
TXER7
TXD75
TXD72
TXCLK7 RXD77
RXD76
RXD71
COL7
TXD67
TXD64
TXD61 GTXCLK6 RXDV6 RXD67
COL6 TESTINT SDA
C
D
RXDV0
RXD07 RXCLK0 RXER0
TXEN7
VSS2.0
VDD3.3
VDD2.0
VSS2.0
VSS3.3
VSS3.3
VSS2.0
VDD2.0 VDD3.3
VSS3.3
VSS3.3
VSS2.0
SCL
MDIO
DMDC
E TXD00 TXCLK0 GTXCLK0 VSS3.3
TXER5
TXEN5
TXD57
TXD56
E
F TXD03 TXD02 TXD01 VSS3.3
VSS2.0
TXD55
TXD54
TXD53
F
G TXD06
TXD05
TXD04
VDD3.3
VDD3.3
TXD50
TXD51
GTXD52
H TXER0
TXEN0
TXD07
VDD2.0
GND
GND
GND
GND
GND
GND
VDD2.0 TXCLK5 RXER5
HRXDV5
J RXD10
CRS1
COL1 VDD3.3
K
RXD13
RXD12
RXD11
VSS2.0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RXCLK5 GTXCLK5 RXD57
RXD56
J
VDD3.3
RXD55
RXD54
KRXD53
L RXD17 RXD16 RXD15 RXD14
GND
GND
GND
GND
GND
GND
VSS3.3
RXD52
RXD51
RXD50
L
M
RXDV1
RXCLK1 GTXCLK1 VDD3.3
GND
GND
GND
GND
GND
GND
VDD3.3 TXEN4 COL5
MCRS5
N
RXER1
TXCLK1
TXD10
VDD2.0
GND
GND
GND
GND
GND
GND
VDD2.0
TXD46
TXD47
NTXER4
P TXD11
TXD12
TXD13
VDD3.3
VDD3.3
TXD43
TXD44
PTXD45
R TXD16
TXD15
TXD14
VSS3.3
VSS2.0
TXD40
TXD41
RTXD42
T TXD17 TXER1 TXEN1 VSS2.0
RXCLK4
RXDV4 GTXCLK4 TXCLK4
T
U GTXCK RESET
SYSCK SELSCK VSS3.3
VSS3.3
VDD3.3 VDD2.0 VDD3.3
VSS3.3
VSS3.3 VDD3.3 VDD2.0 VDD3.3
VSS3.3
VSS2.0
RXD45
RXD46
RXD47
URXER4
V VDD18PLL
BCSTLED
OVUNLED
RXD24
W CRS2
RXD20
COL2
RXD25
RXD27 RXCLK2 TXD22
RXDV2 GTXCLK2 TXD21
TXD23 TXEN2
TXD24 TXD27
COL3
CRS3
RXD30 RXD35 RXD36 RXCLK3 TXD31
RXD31 RXD34 RXD37 TXCLK3 TXD30
TXD32
TXD33
TXD35
COL4
CRS4
VRXD44
TXD36
TXEN3
RXD40
WRXD43
Y RXD21
RXD22
RXD23
RXD26
RXER2 TXCLK2 TXD20
TXD25
TXD26
TXER2
RXD32
RXD33
RXDV3 GTXCLK3 RXER3
TXD34
TXD37
TXER3
RXD41
YRXD42
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Top View
Confidential.
Copyright © 2003, IC Plus Corp.
5/53
August 1, 2003
TC9208M-DS-R06

5 Page





TC9208M arduino
TC9208M
Preliminary Data Sheet
Pin Listing (continued)
No. Pin label
V7 TxData2_2
PriBndw0
W7 TxData2_1
PriClass2_1
Y7 TxData2_0
PriClass0_0
V9 TxEn2
W6 GTxClk2
F17 Vss 2.0
Y10 TxEr2
Y6 TxClk2
W1 Crs2
W3 Col2
Y5 RxEr2
K17 Vdd 3.3
V6 RxClk2
W5 RxDv2
W2 RxData2_0
Y1 RxData2_1
Y2 RxData2_2
D16 Vss 3.3
Y3 RxData2_3
V4 RxData2_4
W4 RxData2_5
Y4 RxData2_6
V5 RxData2_7
Type
I/Opu
I/Opd
I/Opu
O
O
G
I/Opd
I
Is
Is
Is
P
I
Is
Is
Is
Is
G
Is
Is
Is
Is
Is
Description
GMII/MII transmit data - bit 2
Priority bandwidth configuration pins. These configuration pins allow
the bandwidth percentage assigned to a priority packet queue to be
modified to certain hardwired levels. PriBndw chooses between 4
hardwired spreading percentage schemes among the 4 priority
queues of each port.
PriBndw(0)is latched on reset
GMII/MII transmit data - bit 1
PriClass[2] is latched on reset
Priority class - most significant bit.
GMII/MII transmit data - least significant bit
Priority class - least significant bit. Sets priority level per port basis.
PriClass[2] - '00' - port 2 low priority
PriClass[2] - '01' - port 2 has normal priority
PriClass[2] - '10' - port 2 has high priority
PriClass[2] - '11' - port 2 has very high priority
PriClass[2] is latched on reset
GMII/MII transmit enable
GMII transmit clock
Digital ground for core
Transmit Error
MII transmit clock
MII carrier sense indication
MII collision indication
Receive Error
Digital +3.3V power supply for I/O
MII receive clock
GMII/MII data valid
GMII receive data - least significant nibble.
MII receive data
GMII receive data - least significant nibble.
MII receive data
GMII receive data - least significant nibble.
MII receive data
Digital ground for I/O
GMII receive data - least significant nibble.
MII receive data
GMII receive data - most significant nibble
GMII receive data - most significant nibble
GMII receive data - most significant nibble
GMII receive data - most significant nibble
Confidential.
Copyright © 2003, IC Plus Corp.
11/53
August 1, 2003
TC9208M-DS-R06

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