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PDF TC35274 Data sheet ( Hoja de datos )
| Número de pieza | TC35274 | |
| Descripción | TOSHIBA MPEG-4 Video Decoder LSI | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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Preliminary
MPEG-4 Video Decoder LSI
TC35274
TOSHIBA MPEG-4 Video Decoder LSI
TC35274
Tentative Technical Data Sheet
MPEG-4 Video Decoder LSI
Features
U A single-chip MPEG-4 video decoder LSI performs
15frames/sec of MPEG-4 video decoding with QCIF
(176x144 pixels) at 30MHz clock frequency.
U A 4-Mbit embedded DRAM is integrated to reduce
power consumption without performance
degradation.
U An MPEG-4 video core consists of a 16-bit RISC
processor and dedicated hardware accelerators so
as to bring programmability, high performance, and
P-FBGAxxxx
low power consumption.
U Firmware program for the RISC is downloaded into the embedded DRAM before starting
operation. Other applications, such as H.263, are performed by using appropriate firmware.
U General host interface is adopted in order to support various host CPU.
• TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the
responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a
malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing
your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor
Reliability Handbook.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is
assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
• The circuit contained herein is presented only as a guide for the applications, and it is not guaranteed.
TOSHIBA Confidential
1/13
2000-4-27
Version 0.90
1 page  
Preliminary
MPEG-4 Video Decoder LSI
TC35274
Signal Name
/RESET
STANDBY
In/Out
In
In
Table 1. System Control Signals
Bit Width
1
1
Description
System Reset Input (Low Active). When the LSI is reset, this terminal has
to be low for more than 16 clock cycles. When power on, the LSI has to be
reset after PLL locked. It takes approximately 100us until the PLL locked.
System Standby Input (High Active).
Stop clock distribution to the LSI. After standby, system reset is required.
“0” : Active.
“1” : Standby.
Table 2. PLL Control Signals
Signal Name
PLLFN
PLLDIV[2:0]
PLLAVD
PLLAVS
In/Out
In
In
In
In
Bit Width
1
3
1
1
Description
Reference Clock Input.
It has to be 13.00MHz to 20MHz with +/- 10% duty.
System clock frequency select. System Clock = PLLFN * N.
“00” : N=1.0.
“01” : N=1.5.
“10” : N=2.0
“11” : N=2.5.
Analog PLL Power(VDD).
Analog PLL Ground(VSS).
Signal Name
/HCS
/HWR
/HRD
HADDR[6:0]
HDAT[15:0]
HWAIT
HINT
In/Out
In
In
In
In
In/Out
Out
Out
Bit Width
1
1
1
7
16
1
1
Table 3. Host Interface
Description
Chip enable input ( low active).
“0” : Chip select.
“1” : Non operation.
Write strobe (low active).
“0” : Write operation.
“1” : Non operation.
Read Strobe (low active).
“0” : Read operation.
“1” : Non operation.
Address signal.
Data signal.
Bus wait signal (low active).
“0” : Wait.
“1” : Non wait.
Interrupt signal (high active).
“0” : Non operation.
“1” : Interrupt Operation.
Table 4 Video Display Interface
Signal Name
DISPCLK
/DISPHSYNC
/DISPVSYNC
/DISPBLK
DISPPIXEL
In/Out
In
In
In
Out
Out
Bit Width
1
1
1
1
8
Description
Clock signal from display.
HSYNC signal from display.
VSYNC signal form display.
Blanking signal to display.
Luminance (Y) and chrominance (Cb,Cr) signal output.
TOSHIBA Confidential
5/13
Version 0.90
2000-4-27
5 Page 
Preliminary
MPEG-4 Video Decoder LSI
TC35274
Table 7 Host Interface Timing
Parameters
Description
TCSS
TCSH
TADS
TADH
TWTAD
TWTID
TACS
TACID
TDTOD
TDTVD
TDTRS
TDTwS
tDTID
TRDH
TRR
Setup time of HCS.
Hold time of HCS.
Setup time of Address.
Hold time of Address.
Delay time of /HWAIT for /HRD or /HWR.
Access time in handshake access mode.*
Access time in synchronized access mode.
Delay time of HACK
Delay time of Data.
Data hold time.
Read data setup time.
Write data setup time.
Data hold time.
Hold time of /HRD.
Recovery time of /HRD or /HWR
* TSYSCLK means the cycle time of TC35274 internal system clock.
Min
0.0
0.0
0.0
0.0
*3TSYSCLK
*3TSYSCLK
*2TSYSCLK
*1TSYSCLK
0.0
0.0
*3TSYSCLK
Max
15.0
TSYSCLK*100
15.0
15.0
*99TSYSCLK
15.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Access to internal DRAM requires Tsysclk*100 (ns) in a worst case. As for the others accesses, it
takes 3 cycles of the internal system clock.
TOSHIBA Confidential
11/13
Version 0.90
2000-4-27
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet TC35274.PDF ] | |
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