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PDF STU2071 Data sheet ( Hoja de datos )

Número de pieza STU2071
Descripción 4B3T U INTERFACE CIRCUIT
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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STU2071
4B3T TWO-WIRE U INTERFACE CIRCUIT
FOR LT AND NT APPLICATION
120 kbaud LINE SYMBOL RATE (120 SYM-
BOLS PER FRAME)
SCRAMBLER AND DESCRAMBLER AC-
CORDING TO CCITT REC V.29
BARKER CODE (11 SYMBOLS) SYNCHRO-
NIZATION WORD
UNSCRAMBLED 1 KBIT/S HOUSEKEEPING
CHANNEL
ADAPTIVE ECHO CANCELLATION WITH
TRANSVERSAL FILTERING
ADAPTIVE DECISION FEEDBACK EQUALI-
ZATION
AUTOMATIC GAIN CONTROL
PDM AD CONVERTER
AUTOMATIC ACTIVATION AND DEACTIVA-
TION WITH POLARITY ADAPTION
AUTOMATIC CODE VIOLATION DETECTION
POWER FEED UNIT CONTROL
ADVANCED CL3 1.5µm CMOS PROCESS
28 PIN DUAL-IN-LINE PLASTIC PACKAGE
V* DIGITAL INTERFACE
4B3T U INTERFACE CIRCUIT
PRELIMINARY DATA
DIP28
ORDERING NUMBER: STU2071B1
PLCC28
ORDERING NUMBER: STU2071FN
SYSTEM OVERVIEW
STU2071 (UIC) provides two transparent 64 kbit/s
B channels, a transparent 16 kbit/s D channel, a
transparent 1 kbit/s service channel and a 1 kbit/s
maintenance channel for loop and error mes-
sages on subscriber lines.
UIC enables full duplex continuous data transmis-
sion via the standard twisted pair telephone ca-
ble. Adaptive Echo cancellation is used to restore
the received data. An equalizer, done with an
adaptive filter, restores the data which are dis-
torted by the transmission line.
The coefficient of the equalizer and echo cancel-
ler are conserved during a power down. An all
digital PLL performs both bit and frame synchroni-
zation.
The analog front end consists of receive path RX
and transmit path TX, providing a full duplex ana-
log interfacing to the twisted pair telephone cable.
Before data are converted to analog signals, they
pass through a digital filter (TX-filter) to reduce
the high frequency components. After D/A con-
version the signal is amplified and sent to the hy-
brid.
The received signal is converted back to digital
data and passed through the RX matching filter to
restore the line signal. The A/D convertor is a
second order sigma/delta modulator which oper-
ates with a clock of 15.36 MHz. After timing re-
covery, achieved by a digital PLL, the received
signal is equalized, in an adaptive digital filter, to
correct for the frequency and group delay distor-
tion of the line.
Power supply status can be read via PFOFF. The
UIC can disable its power supply (DISS), and two
relay drivers outputs are provided (accessible via
B2*) to control the power feed unit (RD1,RD2).
September 1994
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1 page




STU2071 pdf
NT mode
Figure 3: LT Schematic Application Diagram
STU2071
DIN:
DOUT:
CL:
FR:
XTAL1/2:
CLS:
Data input, datarate = 256 kbit/s, continuous
Data output, datarate = 256 kbit/s, continuous
Data clock input, f = 512 KHz
Frame clock input, f = 8 KHz (1:1)
15.36 MHz Xtal connection (Clock not synchronous to system clock)
Clock output, 7.68 MHz (used to synch S interface)
5/18

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STU2071 arduino
STU2071
LT mode COMMANDS (DIN)
ACT
1000
AL 1 0 0 1
L2 1 0 1 0
LTD 0 0 1 1
DEAC
0000
RES
1101
SSP
0101
L4 1 0 1 1
LT mode INDICATION (DOUT)
ACT
1000
RDS
0111
CT 1 1 0 0
DEAC
DC
RSYN
HI
0001
1111
0100
0011
Activate.
UIC is set in power-up state, executing the complete activation of Layer 1. The
transparent channel transmission is enabled.
Analog Loop.
The analog transmitter output is looped back to the receiver input which is
disconnected from UK0 interface. A pseudo wake-up procedure is executed.
Loop 2.
Command to close Loop 2 in NT.
Line Transmission Disabled.
UIC stops transmitting signals on the line and is powered down.
Deactivate.
Request to deactivate UK0.
Reset.
Reset the UIC to the initial state.
Send Single Pulse.
The UIC transmits single pulse at 1 ms time intervals with alternate polarity.
Repeter loop
Activation running.
UIC is powered-up and the activation procedure is running.
Running Digital Sum.
Given during activation procedure. The receiver has reached synchronization.
Connection Through.
Layer 1 activation procedure has been completed. B and D channels are
transparently connected.
Deactivation running.
UIC is deactivating in response of a DEAC, RES or LTD command.
Deactivation confirmation.
UIC has completed the deactivation procedure.
Resynchronization.
The receiver has lost framing and is attempting to resynchronize.
High Impedance.
When pin PFOFF is HIGH indication HI is output and UIC starts transmitting
INFO U0. Normally used to indicate that remote feeding has been switched off.
POWER DOWN STATE
Power consumption of most functions is reduced;
module interface is not active; C/I messages can-
not be exchanged.
OSCILLATOR
Oscillators of 15.36 MHz are required. When in
NT a tollerances of +/-30 ppm is allowed, it is ad-
visable to use in LT a tollerances of +/-20 ppm.
ACTIVATION DEACTIVATION
The ACTIVATION procedure consists of three
steps: AWAKE, SYNCHRONIZE and CONNECT
THROUGH.
Activation times are (max):
COLDSTART 1 sec
WARMSTART 170 msec
The DEACTIVATION procedure consists of two
steps: line DEACTIVATION and POWER DOWN.
Deactivation time is (typ) 4 ms.
LINE RANGE
The LINE RANGE depends on the cable section.
Typically:
up to 4.2Km with 0.4mm cable
- 5.5Km - 0.5mm -
- 8.0Km - 0.6mm -
Assumed noise level for such performances is
10uV/SQRT(Hz) on a 200KHz bandwidth.
LT CLOCK JITTER
The phase jitter between Master Clock
(15.36MHz) and interface clock (4.096MHz)
should not exceed 50ns.
11/18

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