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PDF KM736V687A Data sheet ( Hoja de datos )
| Número de pieza | KM736V687A | |
| Descripción | 64Kx36-Bit Synchronous Burst SRAM | |
| Fabricantes | Samsung Semiconductor | |
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KM736V687A
Document Title
64Kx36-Bit Synchronous Burst SRAM
Revision History
Rev. No. History
0.0 Initial draft
0.1 Change DC Characteristics.
ICC value from 320mA to 250mA at -7.
ICC value from 300mA to 230mA at -8.
ICC value from 280mA to 200mA at -9.
ISB value from 90mA to 70mA at -7.
ISB value from 80mA to 60mA at -8.
ISB value from 70mA to 50mA at -9.
ISB1 value from 30mA to 20mA
ISB2 value from 30mA to 20mA
1.0 Final spec release.
2.0 Add VDDQ Supply voltage( 2.5V )
3.0 Min tOH Parameter Change : from 2.0ns to 3.0ns
Min tLZC Parameter Change : from 0ns to 3ns
64Kx36 Synchronous SRAM
Draft Date
July. 03. 1998
Sep. 14. 1998
Remark
Preliminary
Preliminary
Nov. 16. 1998
Dec. 02. 1998
Dec. 17. 1998
Fianl
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - December 1998
Rev 3.0
1 page  
KM736V687A
64Kx36 Synchronous SRAM
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADS ADV WRITE CLK ADDRESS ACCESSED
HXXXLX X ↑
L LXLXX X ↑
N/A
N/A
LXHLXX X ↑
N/A
L LXXLX X ↑
N/A
LXHXLX X ↑
N/A
LHL LXX X ↑
LHLHLX L ↑
LHLHLX H ↑
XXXHHL H ↑
HXXXHL H ↑
XXXHHL L ↑
External Address
External Address
External Address
Next Address
Next Address
Next Address
HXXXHL L ↑
Next Address
XXXHHH H ↑
Current Address
HXXXHH H ↑
Current Address
XXXHHH L ↑
Current Address
HXXXHH L ↑
Current Address
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
Operation
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
WRITE TRUTH TABLE
GW
BW
WEa
WEb
WEc
WEd
HHX X X X
H L HHHH
HL LHHH
H L H L HH
HLHHL L
HL LLLL
LXXXXX
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
- 5 - December 1998
Rev 3.0
5 Page 
KM736V687A
64Kx36 Synchronous SRAM
- 11 -
December 1998
Rev 3.0
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet KM736V687A.PDF ] | |
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