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PDF M65582AMF-XXXFP Data sheet ( Hoja de datos )
| Número de pieza | M65582AMF-XXXFP | |
| Descripción | NTSC TV Signal Processor with MCU | |
| Fabricantes | Renesas Technology | |
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M65582AMF-XXXFP
NTSC TV Signal Processor with MCU
REJ03F0093-0100Z
Rev.1.0
Sep.19.2003
Features
• 1package solution with TV baseband signals (Video and Chroma) processor, deflection and 8bit MCU
• High quality picture by 2 Dimension Adaptive Y/C Separation of 3 Line type
• Built-in VM (Velocity Modulation) circuit emphasizing the picture outline by the changing of the Scanning Speed
• Built-in the correction circuits of the picture distortion which is EAST-WEST function etc. for Flat TV
• Available to use the software for best saled MCU M37272
• Available to input External Video signal, S Video signal and Component Video signal
• High performance OSD function with CCD and Half Tone Display
• Analog Video Switch with 5 Video Inputs Composite Video : 3ch, S Video : 1ch, Component Video : 1ch
• Built-in a high performance Blackstrech
• Built-in YNR
• Built-in 8bit MCU core M37272
ROM : 60Kbyte, RAM : 2048byte
Applications
NTSC color television receivers
Rev.1.0, Sep.19.2003, page 1 of 45
1 page  
M65582AMF-XXXFP
Absolute maximum ratings
Parameter
Supply voltage (MCU : 5V)
Supply voltage (ASIC : 3.3V)
Input Voltage (MCU)
Output Voltage (MCU)
Circuit current (MCU)
Circuit current (P00-P07, P10,
P15, P16, P20-P27, P40-P45)
Circuit current (P11-P14)
Circuit current (P24-P27)
Digital input voltage
Analog output current
Power dissipation
Thermal derating
Operating temperature
Storage temperature
Symbol
VDD (MCU)
VDD (ASIC)
VI (MCU)
VO (MCU)
IOH (MCU)
IOL1 (MCU)
IOL2 (MCU)
IOL3 (MCU)
VID (ASIC)
IOUT (ASIC)
Pd
Kt
Topr
Tstg
Ratings
−0.3 to 6.0
−0.3 to 4.0
−0.3 to Vcc+0.3
−0.3 to Vcc+0.3
0 to 1 (See note 1)
0 to 2 (See note 2)
Unit
V
V
V
V
mA
mA
Conditions
All voltage are based
on Vss.Output
transistors are cut off.
0 to 6 (See note 2)
10 (See note 3)
−0.3 to Vcc+0.3
−30
2000
20.0
−20 to 70
−40 to 125
mA
mA
V
mA
mW
mW/°C
°C
°C
Recommended Conditions
Parameter
Supply voltage (MCU) (See note 4)
Supply voltage (Digital)
Supply voltage (Input)
Supply voltage (Output)
Supply voltage (VCXO)
Supply voltage (DEF)
Supply voltage (MCU)
High Iutput voltage P00-P07, P10-P16, P20-
P27,
P40-P45, RESET, X IN
High Iutput voltage SCL1, SCL2, SDA1, SDA2
(When using I2C -Bus)
High Iutput voltage FBP IN
Low Iutput voltage P00-P07, P10-P16, P20-P27
P40-P45
Low Iutput voltage SCL1, SCL2, SDA1, SDA2
(When using I2C-Bus)
Low Iutput voltage (See note 6) RESETB, X IN,
TIM2, TIM3, INT1, INT2, INT3, S IN, S CLK
Low Iutput voltage FBP IN
High average output current (See note 1)
P10-P16, P20-P27, P40-P45
Symbol
VDD (MCU)
VDD (Digital)
VDD (Input)
VDD (Output)
VDD (VCXO)
VDD (DEF)
VSS (MCU)
VIH1 (MCU)
VIH2 (MCU)
VIH3 (ASIC)
VIL1 (MCU)
VIL2 (MCU)
VIL3 (MCU)
VIL4 (ASIC)
IOH (MCU)
Limits
Min.
4.75
3.13
3.13
3.13
3.13
3.13
0
0.8 VDD
(Ta=25 to 70°C, Unless otherwise noted)
Typ.
5.0
3.3
3.3
3.3
3.3
3.3
0
Max.
5.25
3.47
3.47
3.47
3.47
3.47
0
VDD
Unit
V
V
V
V
V
V
V
V
0.7 VDD
0.8 VDD
0
0
0
0
VDD
VDD
0.4 VDD
0.3 VDD
0.2 VDD
0.2 VDD
1
V
V
V
V
V
V
mA
Rev.1.0, Sep.19.2003, page 5 of 45
5 Page 
M65582AMF-XXXFP
Sub
address
Data
Bit
Function
Description
30h D5-D6 2 14H CLK DLY
4fsc clock delay adjust (0: none –— 3: delay)
D7 1 INV 14H CLK
4fsc clock polarity (0: none, 1: invert)
32h D1 1 UV LPF ON
UV LPF (digital) enable
D2 1 ABL SEL
ABL function (0: enable, 1: disenable)
D6 1 VJP SW
Jump SW enable
D7 1 VJP Width
Jump pulse width (0: normal, 1: wide +2-line)
33h D0-D3 4 Black Stretch Time 2 Black stretch recover time (0: slow –— F: fast)
D4-D7 4 Black Stretch Time 1 Black stretch attack time (0: slow –— F fast)
34h D2-D3 2 ABL Speed
ABL processing speed (0: X1, 1: X2, 2: X4, 3: X8)
D4 1 DS D/A Dither
∆Σ D/A (for V-Ramp and E-W) dither enable
D5-D6 2 DS D/A CLK CTL
∆Σ D/A (for V-Ramp and E-W) clock select (0: 28M, 1: 24M, 2: 14M, 3: 16M)
35h D0-D3 4 ABL ASPE
ABL attack speed (0: slow –— 7: fast)
D4-D7 4 ABL SPE
ABL recover speed (0: slow –— 7: fast)
36h D0-D3 4 ABL Gain
ABL gain control (0: minimum –— 7: maximum)
D4-D6 3 ABL Time Constant ABL time constant (0: slow –— 7: fast)
37h D0-D1 2 ABL ASPE 2
ABL attack speed 2 (0: slow –— 7: fast)
D2 1 UV Dither ON
UV dither enable
D3-D5 3 UV Dither Test Enable UV dither test select
38h D0-D5 6 AKB P
AKB reference pulse height (00: minimum –— 3F: maximum)
D6 1 EHT Gain
EHT gain up (0: normal, 1: high)
D7 1 AKB Mode
AKB mode select (0: differential mode, 1: absolute mode)
39h D0 1 YCS HBPF Front
Y/C separation front BPF band width (0: wide, 1: narrow)
D1-D2 2 YCS HBPF Back
Y/C separation rear BPF band width (0: none, 1: wide –— 2 and 3: narrow)
3Ah D0-D5 6 Sharpness Overshoot Gain Sharpness overshoot gain (00: soft –— 3F: sharp)
3Bh D0-D5 6 Sharpness Preshoot Gain Sharpness preshoot gain (00: soft –— 3F: sharp)
3Dh D0 1 Black Stretch SW
Black stretch SW (0: disenable, 1: enable)
D1-D3 3 Black Stretch Depth Black stretch depth (0: shallow –— 7: deep)
D6 1 BS T2 IF ON
Black stretch recover time constant (0: slow, 1: fast)
D4-D5 10 THR NZV
Noise detection threshold level in field (000: minimum –— 3FF: maximum)
3Eh D0-D7
3Fh D0-D7 16 THR NZH
Noise detection threshold level in line (0000: minimum –— FFFF: maximum)
40h D0-D7
41h D0-D6 7 Killer Level
Color Killer threshold level (00: deep –— 7F: shallow)
42h D0-D5 6 RRAY
R-Y phase offset (00: 0˚ –— 3F: 90˚)
D6-D7 2 AMP CTL
Analog ACC amp maximum gain (0: 0dB –— 3: +30dB)
43h D0-D7 9 AMP1 OFF
Analog ACC amp #1 on –>off level (000: minimum –— 1FF: maximum)
44h D7
D0-D6 7 AMP1 ON
Analog ACC amp #1 off –>on level (00: minimum –— 7F: maximum)
45h D0-D3 4 MV
Macro vision (burst) detect level
D4 1 MV1 SW
Macro vision (burst) detect enable
D5 1 MV2 SW
Macro vision (burst) detect position
D6 1 ACC SW
ACC enable
46h D0-D4 5 BGP POS
BGP (for chroma decoder) position
D5 1 Killer SW
Killer detector mode select (0: synchronous detect, 1: amplitude detect)
D6 1 HD SW
HD out (for OSD) select (0: FBP, 1: AFC1 pulse)
D7 1 4FSC SW
A/D-LOGIC clock swap
47h D0-D1 2 AVE SEL
Chroma decoder time constant (0: 32H, 1: 16H, 2: 8H, 3: 1H)
D2-D3 2 C Delay
Chroma delay time (0: none –— 3: delay)
D4 1 OSD Limit
OSD limit select
D6 1 Clamp BITSEL
Y digital clamp time constant (0: fast, 1: slow)
D7 1 Force Killer
Forced killer
48h D0-D1 2 B2 AVE SEL
Accumulation time control of demodulation
D2-D3 2 AMP TIM
Analog ACC hysteresis select
D4-D6 3 V Mask Time
V masking time for demodulation
D7 1 AMP3 ACC
ACC maximum gain
49h D0-D3 4 Free Run Offset
VCXO free-run frequency adjust
D4 1 UV Gain
U/V gain up
D5 1 YUV UV Inv.
U/V invert
D6 1 YUV CXUV
YC/YUV select
D7 1 YUV MPX SEL
U/V multiplex select (0: 2fsc, 1: fsc)
4Bh D0-D1 2 Killer Threshold
PLL stop burst level
4Ch D0-D5 6 BG Start
BGP (for PLL) timing control
D6 1 Free Run
VCXO force free-run
D7 1 SWAP
Burst PLL polarity (0: reverse, 1: normal)
4Dh D0-D1 2 BW DET
PLL Killer threshold level
Note
V Latch
V Latch
Rev.1.0, Sep.19.2003, page 11 of 45
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M65582AMF-XXXFP.PDF ] | |
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