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PDF BC41B143A-ds-001Pe Data sheet ( Hoja de datos )

Número de pieza BC41B143A-ds-001Pe
Descripción Blue Core ROM
Fabricantes CSR　
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No Preview Available ! BC41B143A-ds-001Pe Hoja de datos, Descripción, Manual

Device Features
! Fully Qualified Bluetooth v2.0 system
! Enhanced Data Rate (EDR) compliant with
v2.0.E.2 of specification for both 2Mbps and
3Mbps modulation modes
! Full Speed Bluetooth Operation with Full
Piconet Support
! Scatternet Support
! 1.8V core, 1.7 to 3.6V I/O split rails
! Low Power 1.8V Operation
! Small footprint 6 x 6mm 84-ball VFBGA
Package
! Minimal External Components Required
! Integrated 1.8V regulator
! USB and Dual UART Ports to 3MBaud
! Support for 802.11 Coexistence
! RoHS Compliant
_äìÉ`çêÉ»QJolj
Single Chip Bluetooth® v2.0 System
with EDR
Production Data Sheet for
BC41B143A
July 2005
General Description
_äìÉ`çêÉQJolj is a single chip radio and
baseband IC for Bluetooth 2.4GHz systems
including enhanced data rates (EDR) to 3Mbps.
With the on-chip CSR Bluetooth software stack it
provides a fully compliant Bluetooth system to v2.0
of the specification for data and voice
communications.
Applications
! Cellular Handsets
! Personal Digital Assistants
! Digital cameras and other high volume consumer
products
RAM
SPI
RF IN
RF OUT
2.4
GHz
Radio
ROM
UART/USB
I/O
Baseband
DSP
PIO
MCU
PCM
BlueCore4-ROM has been designed to reduce the number
of external components required which ensures that
production costs are minimised.
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
firmware is fully compliant with the Bluetooth v2.0
Specification (all mandatory and optional features).
To improve the performance of both Bluetooth and
802.11b/g co-located systems a wide range of
co-existence features are available including a variety of
hardware signalling: basic activity signalling and Intel
WCS activity and channel signalling.
XTAL
BlueCore4-ROM System Architecture
BC41B143A-db-001Pe
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 1 of 102

1 page




BC41B143A-ds-001Pe pdf
Status Information
List of Figures
Figure 2.1: BlueCore4-ROM Device Pinout ............................................................................................................ 9
Figure 6.1: BlueCore4-ROM Device Diagram ....................................................................................................... 37
Figure 8.1: BlueCore HCI Stack ............................................................................................................................ 41
Figure 8.2: BlueCore RFCOMM Stack .................................................................................................................. 44
Figure 8.3: Virtual Machine ................................................................................................................................... 46
Figure 9.1: Basic Data Rate and Enhanced Data Rate Packet Structure.............................................................. 48
Figure 9.2: π/4 DQPSK Constellation Pattern ....................................................................................................... 49
Figure 9.3: 8DPSK Constellation Pattern .............................................................................................................. 50
Figure 10.1: Circuit TX/RX_A and TX/RX_B ......................................................................................................... 51
Figure 10.2: Circuit RF_IN .................................................................................................................................... 52
Figure 10.3: Internal Power Ramping.................................................................................................................... 53
Figure 10.4: TCXO Clock Accuracy ...................................................................................................................... 54
Figure 10.5: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 55
Figure 10.6: Crystal Driver Circuit ......................................................................................................................... 57
Figure 10.7: Crystal Equivalent Circuit .................................................................................................................. 57
Figure 10.8: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 60
Figure 10.9: Crystal Driver Transconductance vs. Driver Level Register Setting .................................................. 61
Figure 10.10: Crystal Driver Negative Resistance as a Function of Drive Level Setting ....................................... 62
Figure 10.11: Universal Asynchronous Receiver .................................................................................................. 63
Figure 10.12: Break Signal.................................................................................................................................... 64
Figure 10.13: UART Bypass Architecture ............................................................................................................. 65
Figure 10.14: USB Connections for Self Powered Mode ...................................................................................... 67
Figure 10.15: USB Connections for Bus Powered Mode ...................................................................................... 68
Figure 10.16: USB_DETACH and USB_WAKE_UP Signal .................................................................................. 69
Figure 10.17: Write Operation ............................................................................................................................... 71
Figure 10.18: Read Operation............................................................................................................................... 71
Figure 10.19: BlueCore4-ROM as PCM Interface Master ..................................................................................... 73
Figure 10.20: BlueCore4-ROM as PCM Interface Slave ....................................................................................... 73
Figure 10.21: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 74
Figure 10.22: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 74
Figure 10.23: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 75
Figure 10.24: GCI Interface................................................................................................................................... 75
Figure 10.25: 16-Bit Slot Length and Sample Formats ......................................................................................... 76
Figure 10.26: PCM Master Timing Long Frame Sync ........................................................................................... 78
Figure 10.27: PCM Master Timing Short Frame Sync........................................................................................... 78
Figure 10.28: PCM Slave Timing Long Frame Sync ............................................................................................. 80
Figure 10.29: PCM Slave Timing Short Frame Sync............................................................................................. 80
Figure 10.30: Example EEPROM Connection ...................................................................................................... 84
Figure 10.31: Example TXCO Enable OR Function .............................................................................................. 84
Figure 13.1: Application Circuit for Radio Characteristics Specification with 6 x 6mm VFBGA Package .............. 88
Figure 14.1: BlueCore4-ROM 84-Ball VFBGA Package Dimensions.................................................................... 89
Figure 15.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 90
Figure 17.1: Tape and Reel Orientation ................................................................................................................ 93
Figure 17.2: Tape Dimensions .............................................................................................................................. 94
BC41B143A-ds-001Pe
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 5 of 102

5 Page





BC41B143A-ds-001Pe arduino
6 x 6mm VFBGA Package Information
Test and Debug
RESET
RESETB
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
TEST_EN
PIO Port
PIO[2]
PIO[3]
PIO[4]
PIO[5]
PIO[6]
PIO[7]
PIO[8]
PIO[9]
PIO[10]
PIO[11]
AIO[0]
AIO[1]
AIO[2]
Ball Pad Type
Description
C7
CMOS input with weak
internal pull-down
Reset if high. Input debounced, so must be
high for >5ms to cause a reset
D8
CMOS input with weak
internal pull-up
Reset if low. Input debounced, so must be
low for >5ms to cause a reset
C9
CMOS input with weak
internal pull-up
Chip select for Serial Peripheral Interface,
active low
C10
CMOS input with weak
internal-pull-down
Serial Peripheral Interface clock
C8
CMOS input with weak
internal pull-down
Serial Peripheral Interface data input
B9
CMOS output, tri-state with
weak internal pull-down
Serial Peripheral Interface data output
C6
CMOS input with strong
internal pull-down
For test purposes only (leave unconnected)
Ball Pad Type
Bi-directional with
B3 programmable strength
internal pull-up/down
Bi-directional with
B4 programmable strength
internal pull-up/down
Bi-directional with
E8 programmable strength
internal pull-up/down
Bi-directional with
F8 programmable strength
internal pull-up/down
Bi-directional with
F10 programmable strength
internal pull-up/down
Bi-directional with
F9 programmable strength
internal pull-up/down
Bi-directional with
C5 programmable strength
internal pull-up/down
Bi-directional with
C3 programmable strength
internal pull-up/down
Bi-directional with
C4 programmable strength
internal pull-up/down
Bi-directional with
E3 programmable strength
internal pull-up/down
H4 Bi-directional
H5 Bi-directional
J5 Bi-directional
Description
Programmable input/output line
Programmable input/output line
Programmable input/output line or optionally
BT_Priority/Ch_Clk output for co-existence
signalling
Programmable input/output line or optionally
BT_Active output for co-existence signalling
Programmable input/output line or optionally
WLAN_Active/Ch_Data input for
co-existence signalling
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
BC41B143A-ds-001Pe
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 11 of 102

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