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PDF ICS8308I Data sheet ( Hoja de datos )
| Número de pieza | ICS8308I | |
| Descripción | Low Skew 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS. The
ICS8308I has two selectable clock inputs. The
CLK, nCLK pair can accept most differential input
levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased
from 8 to 16 by utilizing the ability of the outputs to drive two
series terminated transmission lines.
The ICS8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make
the 8308I ideal for those clock distribution applications requiring
well defined performance and repeatability.
FEATURES
• 8 LVCMOS/LVTTL outputs (7Ω typical output impedance)
• Selectable LVCMOS_CLK or differential CLK, nCLK
inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum Output Frequency: 350MHz
• Output Skew: (3.3V± 5%): 100ps (maximum)
• Part to Part Skew: (3.3V± 5%): 1ns (maximum)
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
CLK_EN Pullup
LVCMOS_CLK Pullup
CLK Pullup
nCLK Pulldown
CLK_SEL Pullup
1
0
D
Q
LE
OE Pullup
PIN ASSIGNMENT
Q0 1
24 VDDO
GND 2
23 Q2
CLK_SEL 3
22 GND
LVCMOS_CLK 4
21 Q3
Q0
CLK 5
20 VDDO
nCLK 6
19 Q4
Q1
CLK_EN 7
18 GND
OE 8
17 Q5
Q2
VDD 9
16 VDDO
GND 10 15 Q6
Q3 Q1 11 14 GND
VDDO 12 13 Q7
Q4
ICS8308I
Q5 24-Lead, 300-MIL TSSOP
Q6 4.4mm x 7.8mm x 0.92mm body package
G Package
Q7 Top View
8308AGI
www.icst.com/products/hiperclocks.html
1
REV. B JULY 25, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
TABLE 4F. DC CHARACTERISTICS, VDD, VDDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions Minimum Typical
VIH Input High Voltage
VIL Input Low Voltage
LVCMOS
LVCMOS_CLK
CLK_EN, OE
2
-0.3
I Input Current
IN
VIN = VDD or
VIN = GND
VOH Output High Voltage; NOTE 1
IOH = -15mA
1.8
VOL Output Low Voltage; NOTE 1
IOL = 15mA
VPP
VCMR
Peak-to-Peak Input Voltage CLK, nCLK
Input Common Mode Voltage;
NOTE 2, 3
CLK, nCLK
0.15
GND + 0.5
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.
See Parameter Measurement section, "3.3V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as V .
IH
Maximum
VDD + 0.3
1.3
0.7
300
0.6
1.3
VDD - 0.85
Units
V
V
V
µA
V
V
V
V
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Output Frequency
Propagation
tPD Delay;
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
2
2
350 MHz
4 ns
4 ns
tsk(o) Output Skew; NOTE 3, 7
Measured on
rising edge @VDDO/2
100 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
Measured on
rising edge @VDDO/2
0.8V to 2V
IJ 150MHz, Ref = CLK, nCLK
0.2
45
1 ns
1 ns
55 %
tPZL, tPZH Output Enable Time; NOTE 5
5
tPLZ, tPHZ
tS
Output Disable Time; NOTE 5
Clock Enable
Setup Time;
NOTE 6
CLK_EN to
CLK, nCLK
CLK_EN to
LVCMOS_CLK
5
1
0
tH
Clock Enable
Hold Time;
NOTE 6
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
0
1
NOTE 1: Measured from the differential input crossing point to V /2 of the output.
DDO
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
ns
ns
ns
ns
ns
ns
8308AGI
www.icst.com/products/hiperclocks.html
5
REV. B JULY 25, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS87004I
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3 R4
125 125
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
84 84
3.3V
LVDS_Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
87004AGI
www.icst.com/products/hiperclocks.html
11
REV. B JULY 25, 2005
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS8308I.PDF ] | |
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