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PDF ICS8302 Data sheet ( Hoja de datos )

Número de pieza ICS8302
Descripción LOW SKEW 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8302 is a low skew, 1-to-2 LVCMOS
Fanout Buffer and a member of the
HiPerClockS™ HiPerClock S™ family of High Perfor mance
Clock Solutions from ICS. The ICS8302 has a
single ended clock input. The single ended clock
input accepts LVCMOS or LVTTL input levels. The ICS8302
features a pair of LVCMOS/LVTTL outputs. The ICS8302 is
characterized at full 3.3V for input VDD, and mixed 3.3V and
2.5V for output operating supply modes (VDDO). Guaran-
teed output and part-to-part skew characteristics make
the ICS8302 ideal for clock distribution applications demand-
ing well defined performance and repeatibility.
FEATURES
• 2 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
• Maximum output frequency: 200MHz
• Output skew: 25ps (typical)
• Part-to-part skew: 250ps (typical)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK
8302AM
PIN ASSIGNMENT
Q0
VDDO 1
8 Q0
VDD 2
7 GND
Q1
CLK 3
6 VDDO
GND 4
5 Q1
ICS8302
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. C JUNE 15, 2004

1 page




ICS8302 pdf
Integrated
Circuit
Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2
LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
VDD,
VDDO
LVCMOS
GND
SCOPE
Qx
VDD
VDDO
LVCMOS
GND
SCOPE
Qx
-1.65V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
-1.25V±5%
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1
Qx
PART 2
Qy
V
DD
2
V
DD
2
t sk(pp)
PART-TO-PART SKEW
V
DDO
Qx 2
V
DDO
Qy 2
t sk(o)
OUTPUT SKEW
20%
Clock
Outputs
80%
tR
80%
tF
20%
CLK
Q0, Q1
VDD
2
VDDO
2
t
PD
OUTPUT RISE/FALL TIME
Q0, Q1
VDDOX
2
t PW
VDDOX
2
t PERIOD
odc = t PW
t PERIOD
OUTPUT PULSE WIDTH/PERIOD
8302AM
VDDOX
2
PROPAGATION DELAY
www.icst.com/products/hiperclocks.html
5
REV. C JUNE 15, 2004

5 Page










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