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PDF TDA9112A Data sheet ( Hoja de datos )
| Número de pieza | TDA9112A | |
| Descripción | HIGH-END I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR | |
| Fabricantes | ST Microelectronics | |
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TDA9112A
HIGH-END I²C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
• Advanced I2C-bus controlled deflection
processor dedicated for high-end CRT monitors
• Single supply voltage 12V
• Very low jitter
• DC/DC converter controller
• Advanced EW drive
• Advanced asymmetry corrections
• Automatic multistandard synchronization
• 2 dynamic correction waveform outputs
• X-ray protection and Soft-start & stop on
horizontal and DC/DC drive outputs
• I2C-bus status register
Horizontal section
• 150 kHz maximum frequency
• Corrections of geometric asymmetry: Pin
cushion asymmetry, Parallelogram, separate
Top/Bottom corner asymmetry
• Tracking of asymmetry corrections with vertical
size and position
• Fully integrated horizontal moiré cancellation
Vertical section
• 200 Hz maximum frequency
• Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
• Vertical size and position prescales for factory
adjustment
• Vertical moiré cancellation through vertical
ramp waveform
• Compensation of vertical breathing with EHT
variation; I2C-bus gain adjustment
EW section
• Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately, S-
and W-corrections
• Horizontal size adjustment
• Tracking of EW waveform with Vertical size and
position, horizontal size and frequency
• Compensation of horizontal breathing with EHT
variation, I2C-bus gain adjustment
Dynamic correction section
• Generates waveforms for dynamic corrections
like focus, brightness uniformity, ...
• 1 output with vertical dynamic correction
waveform, both polarities, tracking with vertical
size and position
• 1 output with composite HV dynamic correction
waveform, both polarities, shape control on
horizontal waveform component, tracking with
horizontal size
DC/DC controller section
• Step-up and step-down conversion modes
• External sawtooth configuration
• I2C-bus-controlled output voltage
• Synchronized on hor. frequency with phase
selection
• Selectable polarity of drive signal
• Protection at H unlock condition
DESCRIPTION
The TDA9112A is a monolithic integrated circuit
assembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preampli-
fier, video amplifier, OSD controller), the
TDA9112A allows fully I2C bus-controlled compu-
ter display monitors to be built with a reduced
number of external components.
SDIP 32 (Shrink DIP package)
ORDER CODE: TDA9112A
October 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
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1
1 page  
H/HVSyn 1
HLckVBk 3
SDA 31
SCL 30
Vcc 29
RefOut 13
GND 27
HGND
7
HPosF HPLL1F
10 9
RO CO HOscF
86 4
HFly
12
HPLL2C
5
H-sync
detection
Polarity
handling
V-blank
H-lock
I²C-bus
interface
Supply
supervision
Reference
generation
Phase/frequency
comparator
Horizontal position
PLL1 speed
Lock detection
Horizontal
VCO
PLL1
H-moiré controller
H-moiré amplitude
I²C-bus control registers
: Multiple bit djustments
V-sync
extraction
& detection
V-dynamic
correction
(focus, brightness)
VDyCor amplitude
Phase comparator
Phase shifter
H duty controller
Pin cushion asymm.
Parallelogram
Top corner asymm.
Bottom corner asymm.
Hor. duty cycle
PLL2
H-drive
buffer
Safety
processor
B+
DC/DC
converter
controller
B+ ref.
Tracking
HV-dynamic correction
(focus,brightness)
HVDyCor V-amplitude
HVDyCor H-amplitude
HVDyCor H-symmetry
HVDyCor H-shape
26 HOut
25 XRay
28 BOut
16 BISense
15 BRegIn
14 BComp
11 HVDyCor
Internal
ref.
V-sync detection
Input selection
Polarity handling
Vertical oscillator
with AGC
V-ramp control
Vertical size & pos.
Prescale size & pos.
S- & C-correction
Vertical moiré
Breathing gain
2
VSyn
21
VGND
19 20 22
32
VOscF
VCap VDyCor
VAGCCap
23
VOut
18
VEHTIn
17
HEHTIn
EW generator
H size
Pin cushion
Keystone
Top corners
Bottom corners
S-correction
W-correction
Breathing gain
24 EWOut
TDA9112A
5 Page 
TDA9112A
Table 1. Horizontal section ( Vcc = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Picture geometry corrections through PLL1 & PLL2
tHph /TH
Hor. VCO phase vs. sync signal (via
PLL1), see Figure 7
HPOS (Sad01h):
11111111b
10000000b
00000000b
tPCAC /TH
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
PCAC (Sad11h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tParalC /TH
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
PARAL (Sad12h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tTCAC /TH
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
TCAC (Sad13h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tBCAC /TH
BCAC (Sad14h) full span
(9)
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static VPOS at medium
phase (via PLL2), measured in corners VSIZE at minimum
VSIZE at medium
VSIZE at maximum
Min.
Value
Typ.
+11
0
-11
±0.9
±1.6
±2.6
±1.4
±1.9
±2.4
±0.4
±1.4
±3.5
±0.4
±1.4
±3.5
Max.
Units
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
Notes about horizontal section
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate
the free-running frequency is fHO(0)=0.122/(RRO CCO)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500Ω and a resistance to ground of about 20kΩ.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The tph(min) parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
11/60
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA9112A.PDF ] | |
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