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PDF WCFS0808V1E Data sheet ( Hoja de datos )

Número de pieza WCFS0808V1E
Descripción 32K x 8 3.3V Static RAM
Fabricantes Weida 
Logotipo Weida Logotipo



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1WCFS0808V1E
WCFS0808V1E
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— 12/15 ns
• Plastic SOJ and TSOP packaging
Functional Description
The WCFS0808V1E is a high-performance 3.3V CMOS Static
RAM organized as 32K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE) and ac-
tive LOW Output Enable (OE) and three-state drivers. The de-
vice has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
Logic Block Diagram
AAAAAAAAAA1234567890
CE
WE
OE
INPUT BUFFER
32K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
32K x 8 3.3V Static RAM
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The WCFS0808V1E is available in 28-pin stan-
dard 300-mil-wide SOJ and TSOP Type I packages.
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Pin Configurations
SOJ
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A4
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
WCFS0808V1E 12ns
12
55
500
WCFS0808V1E 15ns
15
50
500
Document #: 38-05225 Rev. **
Revised February 11, 2002

1 page




WCFS0808V1E pdf
WCFS0808V1E
Switching Characteristics Over the Operating Range[5] (Continued)
Parameter
Description
READ CYCLE
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
tPU CE LOW to Power-Up
tPD CE HIGH to Power-Down
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[8]
WE HIGH to Low Z[6]
WCFS0808V1E 15ns
Min. Max.
15
15
3
15
6
0
6
3
7
0
15
15
10
10
0
0
10
8
0
7
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
tCDR
tR
VCC for Data Retention
Chip Deselect to Data
Retention Time
Operation Recovery Time
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
Min.
2.0
0
tRC
Max.
Unit
V
ns
ns
Document #: 38-05225 Rev. **
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