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PDF RMBA19500 Data sheet ( Hoja de datos )

Número de pieza RMBA19500
Descripción PCS 2 Watt Linear GaAs MMIC Power Amplifier
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! RMBA19500 Hoja de datos, Descripción, Manual

May 2004
RMBA19500
PCS 2 Watt Linear GaAs MMIC Power Amplifier
General Description
The RMBA19500 is a highly linear Power Amplifier. The
circuit uses our pHEMT process. It has been designed for
use as a driver stage for PCS base stations, or as the
output stage for Micro- and Pico-Cell base stations. The
amplifier has been optimized for high linearity requirements
for CDMA operation.
Features
• 2 Watt Linear output power at 36dBc ACPR1 for CDMA
operation
• Small signal gain of 30dB typ.
• Small outline SMD package
Device
Absolute Ratings
Symbol
Vd
Vg
PRF
TC
TS
Parameter
Drain Supply Voltage1
Gate Supply Voltage
RF Input Power (from 50source)
Operating Case Temperature Range
Storage Temperature Range
Note:
1. Only under quiescent conditions—no RF applied.
Ratings
+10
-5
+5
-30 to +85
-40 to +100
Units
V
V
dBm
°C
°C
©2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C

1 page




RMBA19500 pdf
Figure 4. Layout of Test Evaluation Board (RMBA19500-TD, G655971)
Test Procedure for the Evaluation Board (RMBA19500-TB)
CAUTION: LOSS OF GATE VOLTAGES (Vg1, Vg2,
Vg3) WHILE CORRESPONDING DRAIN VOLTAGES
(Vdd) ARE PRESENT CAN DAMAGE THE AMPLIFIER.
The following sequence must be followed to properly test
the amplifier. (It is necessary to add a fan to provide air
cooling across the heat sink of RMBA19500.)
Step 1: Turn off RF input power.
Step 2: Use GND terminal of the evaluation board for the
ground of the DC supplies. Set Vgg1, Vgg2 and Vgg3 to
-3V (pinch-off).
Step 3: Slowly apply drain supply voltages of +7V to the
board terminal Vdd ensuring that there is no short.
Step 4: Adjust Vgg12 up from -3V until the drain current
(with no RF applied) increases to Idq12 as per supplied
result sheet. Then adjust Vgg3 until the total drain current
becomes equal to the sum of Idq12 and Idq3.
Step 5: After the bias condition is established, RF input
signal may now be applied at the appropriate frequency
band and appropriate power level.
Step 6: Follow turn-off sequence of:
(i) Turn off RF Input Power
(ii) Turn down and off drain voltage Vdd.
(iii) Turn down and off gate voltages Vgg1, Vgg 2 and
Vgg3.
©2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C

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