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PDF M65818AFP Data sheet ( Hoja de datos )
| Número de pieza | M65818AFP | |
| Descripción | Digital Amplifier Processor of S-Master Technology | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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M65818AFP
Digital Amplifier Processor of S-Master* Technology
REJ03F0019-0100Z
Rev.1.00
Sep.04.2003
Description
The M65818AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital
input signal to high precise switching-pulse digital output without analog processing.
The M65818AFP has built-in 24bit sampling rate converter and digital-gain-controller.
The M65818AFP enables to realize high precise (X`tal oscillation precision) fully digital amplifier systems combining
with power driver IC.
Features
• Built-in 24bit Sampling Rate Converter.
Input Signal Sampling Rate
from 32KHz to 192KHz(24bit Maximum).
4 kinds of Digital Input Format.
• Built-in L/R Independent Digital Gain Control.
• Built-in Soft Mute Function with Exponential Approximate-Curve.
• Correspondence for SACD signal (64Fs 1bit,Fs=44.1KHz).
• Direct Output from Sampling Rate Converter.
• 3.3V and 5.0V Power Supply Operation at Output Clock, Input Data, and Control Signal Port
Main Applications
• Master Clock
Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso
• Input Signal Format:
MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)
LSB First Right Justified(24bit),I2S(24bit)
• Input Signal Sampling Rate from 32kHz to 192kHz.
• 8Fs Input Mode: Correspondence for External Digital Filter, Sampling Rate Converter Outputs.
• Gain Control Function:
+30dB~ -∞dB(0.1dB Step until -96dB, -138dB Minimum)
• Third Order ∆Σ (16Fso:6bit/5bit,32Fso: 5bit)
• Sampling Rate Converter Output :MSB First Left justified /Lch,Rch Independent/32BCK
Recommended Operating Conditions
Logic Block:3.3V±10%, PWM Buffer Block : 5.0V±10%
(** "S-Master" is the digital amplifier technology developed by Sony Corporation.
"S-Master" is a trademark of Sony Corporation.
Rev.1.00, Sep.04.2003, page 1 of 38
1 page  
M65818AFP
2. Block Diagram
Rev.1.00, Sep.04.2003, page 5 of 38
5 Page 
M65818AFP
5.2. SCDT, SCSHIFT, SCLATCH
38 37 36
SCDT,SCSHIFT,and SCLATCH are input pins for setting M65818AFP's operation.
Input format of SCDT, SCSHIFT and SCLATCH is shown below.
• Input format of SCDT, SCSHIFT, and SCLATCH.
SCDT
24
SCSHIFT
SCLATCH
20
15
10
5
bit1
1
• Mode Setting
The operating Mode are classified in four and assigned by bit1and bit2. These four functions are shown below.
(bit1 and bit2 ) = ( "L" and "L" ) Gain control mode: Gain control.
(bit1 and bit2 ) = ( "L "and "H" ) System1 Mode: Primary block initialization, etc.
(bit1 and bit2 ) = ( "H" and "L" ) System2 Mode : Secondary block initialization, etc.
(bit1 and bit2 ) = ( "H" and "H" ) Test mode ( setting prohibition )
Refer to Chapter 6 about these four setting in detail.
5.3. DATA, BCK, LRCK
43 44 45
DATA, BCK and LRCK are input pins under condition of `Normal ` mode.
Input formats are supported by following 4 ways, and are set by Serial Control, "System1 Mode, bit3 and bit4".
Input data length are selectable in the case of "MSB First Right Justified"
(Serial Control "System1 Mode, bit5, 6").
and Input Signal Sampling Rate(1/2/4fsi) are set by Serial Control,"System1 Mode, bit7,8"
Input formats are shown in following figures.
Rev.1.00, Sep.04.2003, page 11 of 38
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M65818AFP.PDF ] | |
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