|
|
PDF M470L3223DT0 Data sheet ( Hoja de datos )
| Número de pieza | M470L3223DT0 | |
| Descripción | 256MB DDR SDRAM MODULE | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M470L3223DT0 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
M470L3223DT0
256MB DDR SDRAM MODULE
(32Mx64 based on 32Mx 8 DDR SDRAM)
200pin SODIMM
64bit Non-ECC/Parity
Revision 0.0
Dec. 2001
Rev. 0.0 Dec. 2001
1 page  
M470L3223DT0
Absolute Maximum Rate
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
-1.0 ~ 3.6
-55 ~ +150
V
°C
Power dissipation
PD 12 W
Short circuit current
IOS 50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
mA
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
2.3
2.7 V
I/O Reference voltage
VREF
VDDQ/2-50mV VDDQ/2+50mV
V
1
I/O Termination voltage(system)
Input logic high voltage
VTT
VIH(DC)
VREF-0.04
VREF+0.15
VREF+0.04
VDDQ+0.3
V
V
2
4
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
4
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.3
VDDQ+0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX(DC)
1.15
1.35 V 5
Input leakage current
II -2
2 uA
Output leakage current
IOZ -5
5 uA
Output High Current(Normal strengh driver)
;VOUT = VTT + 0.84V
Output High Current(Normal strengh driver)
;VOUT = VTT - 0.84V
Output High Current(Half strengh driver)
;VOUT = VTT + 0.45V
Output High Current(Half strengh driver)
;VOUT = VTT - 0.45V
IOH -16.8
IOL 16.8
IOH -9
IOL 9
mA
mA
mA
mA
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.0 Dec. 2001
5 Page 
M470L3223DT0
Parameter
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
64Mb, 128Mb
256Mb
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Autoprecharge write recovery +
Precharge time
-TCA2(DDR266A)
Symbol
Min Max
tMRD
15
tDS 0.5
tDH 0.5
tDIPW 1.75
tPDEX
7.5
tXSNR
75
tXSRD
200
tREFI
15.6
7.8
tQH
tHP
-tQHS
-
tHP
tCLmin
or tCHmin
-
tQHS
0.75
tWPST
0.4
0.6
tDAL
(tWR/tCK)
+
(tRP/tCK)
-TCB0(DDR266B)
Min Max
15
0.5
0.5
1.75
7.5
75
200
15.6
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.75
0.4 0.6
(tWR/tCK)
+
(tRP/tCK)
-TCA0 (DDR200)
Min Max
16
0.6
0.6
2
10
80
200
15.6
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.8
0.4 0.6
(tWR/tCK)
+
(tRP/tCK)
Unit Note
ns
ns 7,8,9
ns 7,8,9
ns
ns
ns 4
tCK
us 1
us 1
ns 5
ns
ns
tCK 3
tCK 11
1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.0 Dec. 2001
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet M470L3223DT0.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M470L3223DT0 | 256MB DDR SDRAM MODULE | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |