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PDF M470L3224BT0 Data sheet ( Hoja de datos )
| Número de pieza | M470L3224BT0 | |
| Descripción | 256MB DDR SDRAM MODULE | |
| Fabricantes | Samsung semiconductor | |
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M470L3224BT0
200pin DDR SDRAM SODIMM
256MB DDR SDRAM MODULE
(32Mx64 based on 16Mx16 DDR SDRAM)
200pin SODIMM
64-bit Non-ECC/Parity
Revision 0.1
June. 2001
Rev. 0.1 June. 2001
1 page  
M470L3224BT0
200pin DDR SDRAM SODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
Voltage on VDDQ supply relative to Vss
Storage temperature
VDDQ
TSTG
-0.5 ~ 3.6
-55 ~ +150
Power dissipation
PD 8
Short circuit current
IOS 50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Unit
V
V
V
°C
W
mA
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
;VOUT = VTT + 0.84V
Output High Current(Normal strengh driver)
;VOUT = VTT - 0.84V
Output High Current(Half strengh driver)
;VOUT = VTT + 0.45V
Output High Current(Half strengh driver)
;VOUT = VTT - 0.45V
Symbol
VDD
VDDQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
IOZ
IOH
Min Max
2.3 2.7
2.3 2.7
VDDQ/2-50mV VDDQ/2+50mV
VREF-0.04
VREF+0.04
VREF+0.15
VDDQ+0.3
-0.3 VREF-0.15
-0.3 VDDQ+0.3
0.3 VDDQ+0.6
1.15 1.35
-2 2
-5 5
-16.8
Unit
V
V
V
V
V
V
V
V
uA
uA
mA
IOL 16.8
mA
IOH -9
mA
IOL 9
mA
Note
1
2
4
4
3
5
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 June. 2001
5 Page 
M470L3224BT0
200pin DDR SDRAM SODIMM
Parameter
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
Refresh interval time
64Mb, 128Mb
256Mb
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
-TCA2(DDR266A)
Symbol
Min Max
-TCB0(DDR266B)
Min Max
-TCA0 (DDR200)
Min Max
tMRD
15
15
16
tDS 0.5 0.5 0.6
tDH 0.5 0.5 0.6
tDIPW 1.75
1.75
2
tPDEX
10
10
10
tXSW
95
116
tXSA
75
75
80
tXSR
200
200
200
tREF
15.6
15.6
15.6
7.8 7.8 7.8
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tQHS
0.75
0.75
0.8
tWPST 0.25
0.25
0.25
Unit Note
ns
ns 7,8,9
ns 7,8,9
ns
ns
ns
ns 4
Cycle
us 1
us 1
ns 5
ns
ns
tCK 3
Note : 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DINNs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half
period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.1 June. 2001
11 Page | ||
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