PDF ICSSSTVF16859 Data sheet ( Hoja de datos )

Número de pieza	ICSSSTVF16859
Descripción	DDR 13-Bit to 26-Bit Registered Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICSSSTVF16859 Advance Information DDR 13-Bit to 26-Bit Registered Buffer Recommended Applications: • DDR Memory Modules: - DDRI (PC1600, PC2100) - DDR333 (PC2700) - DDRI-400 (PC3200) • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class I specifications on outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 64 pin TSSOP and 56 pin MLF packages Truth Table1 RESET# L H H H Inputs CLK CLK# X or X or Floating Floating ↑↓ ↑↓ L or H L or H Q Outputs DQ X or Floating L HH LL X Q0(2) Notes: 1. H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care 2. Output level before the indicated steady state input conditions were established. Block Diagram CLK CLK# RESET# D1 VREF R CLK D1 Q1A Q1B Pin Configurations Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 VDDQ 63 GND 62 D13 61 D12 60 VDD 59 VDDQ 58 GND 57 D11 56 D10 55 D9 54 GND 53 D8 52 D7 51 RESET# 50 GND 49 CLK# 48 CLK 47 VDDQ 46 VDD 45 VREF 44 D6 43 GND 42 D5 41 D4 40 D3 39 GND 38 VDDQ 37 VDD 36 D2 35 D1 34 GND 33 VDDQ 64-Pin TSSOP 6.10 mm. Body, 0.50 mm. pitch 56 43 Q7A 1 Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B14 ICSSSTVF16859 42 D10 D9 D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 D5 29 D4 15 28 0776—03/18/03 To 12 Other Channels 56-Pin VFQFN (MLF2) ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. 1 page ICSSSTVF16859 Advance Information DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700) TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL PARAMETERS CONDITIONS VDDQ MIN TYP VIK II = -18mA 2.3V VOH IOH = -100µA 2.3V-2.7V VDDQ - 0.2 IOH = -8mA 2.3V 1.95 VOL IOL = 100µA IOL = 8mA 2.3V-2.7V 2.3V II All Inputs Standby (Static) VI = VDD or GND RESET# = GND 2.7V IDD Operating (Static) VI = VIH(AC) or VIL(AC), RESET# = VDD 25 Dynamic operating (clock only) RESET# = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK# switching 30 50% duty cycle. RESET# = VDD, IO = 0 IDDD VI = VIH(AC) or VIL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half 2.7V 10 clock frequency, 50% duty cycle rOH Output High IOH = -16mA 2.3V-2.7V 7 13.5 rOL Output Low IOL = 16mA 2.3V-2.7V 7 13 rO(D) [rOH - rOL] each separate bit IO = 20mA, TA = 25° C 2.5V Ci Data Inputs CLK and CLK# VI = VREF ±350mV VICR = 1.25V, VI(PP) = 360mV 2.5V 2.5 2.5 Notes: 1 - Guaranteed by design, not 100% tested in production. MAX -1.2 0.2 0.35 ±5 0.01 20 20 4 3.5 3.5 UNITS V µA µA mA µ/clock MHz µA/ clock MHz/data Ω Ω Ω pF 0776—03/18/03 5 5 Page

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ICSSSTVF16859	DDR 13-Bit to 26-Bit Registered Buffer	Integrated Circuit Systems

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