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PDF ICSSSTV16857 Data sheet ( Hoja de datos )

Número de pieza ICSSSTV16857
Descripción DDR 14-Bit Registered Buffer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICSSSTV16857 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICSSSTV16857
DDR 14-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
• Differential clock signal
• Meets SSTL_2 signal data
• Supports SSTL_2 class I & II specifications
• low-voltage operation
VDD = 2.3V to 2.7V
• 48 pin TSSOP package
Truth Table1
Inputs
RESET#
L
H
H
CLK
X or
Floating
CLK#
X or
Floating
H L or H L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q (2)
0
Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1. H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
Block Diagram
CLK
CLK#
RESET#
38
39
34
D1
VREF
48
35
R
CLK
D1
1 Q1
16857 Rev D 07/09/01
Third party brands and names are the property of their respective owners.
To 13 Other Channels
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

1 page




ICSSSTV16857 pdf
ICSSSTV16857
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD=2.5±0.2V
MIN TYP MAX
fclock Clock frequency
tPD Clock to output time
tRST Reset to output time
tSL Output slew rate
Setup time, fast slew rate 2, 4
tSU Setup time, slow slew rate 3, 4
Hold time, fast slew rate 2,4
Th Hold time, slow slew rate 3, 4
133
1.1 2.4
3.1
1 1.5
Data before CKD , CK#E 0.75 0.018
0.9
Data after CKD , CK#E
0.75 0.145
0.9
200
2.8
5
4
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate =1V/ns.
4 - CLK, CLK# signals input slew rates are =1V/ns.
3 - For data signal input slew rate =0.5V/ns and < 1V/ns.
UNITS
MHz
ns
ns
V/ns
ns
ns
ns
ns
Sw itching Characteristics
(over recom m ended operating free-air tem perature range, unles s otherwis e noted)
SYMBOL
From
To
VD D = 2 .5 ± 0 .2 V
(In p u t)
(Ou tp u t)
MIN TYP MAX
fclock
tPD
tph1
CLK, CLK#
RESET#
133 200
Q 1.1 2.4 2.8
Q 3.1 5
U N ITS
MH z
ns
ns
Third party brands and names are the property of their respective owners.
5

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