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PDF ICSSSTV16859 Data sheet ( Hoja de datos )

Número de pieza ICSSSTV16859
Descripción DDR 13-Bit to 26-Bit Registered Buffer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICSSSTV16859 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICSSSTV16859
Preliminary Product Preview
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class II specifications on outputs
• low-voltage operation
- VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF2 packages
Truth Table1
RESET#
L
H
H
H
Inputs
CLK
CLK#
X or
Floating
­
­
X or
Floating
¯
¯
L or H L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q0(2)
Notes:
1. H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
CLK
CLK#
RESET#
48
49
51
D1
VREF
35
45
Block Diagram
R
CLK
D1
16 Q1A
32 Q1B
To 12 Other Channels
Pin Configurations
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64 VDDQ
63 GND
62 D13
61 D12
60 VDD
59 VDDQ
58 GND
57 D11
56 D10
55 D9
54 GND
53 D8
52 D7
51 RESET#
50 GND
49 CLK#
48 CLK
47 VDDQ
46 VDD
45 VREF
44 D6
43 GND
42 D5
41 D4
40 D3
39 GND
38 VDDQ
37 VDD
36 D2
35 D1
34 GND
33 VDDQ
64-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
56
Q7A 1
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B14
15
ICSSTV16859
43
42 D10
D9
D8
D7
RB
GND
CLKB
CLK
VDDQ
VDDI
VREF
D6
D5
29 D4
28
56 pin MLF2
16859 Rev B 06/22/01
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

1 page




ICSSSTV16859 pdf
ICSSSTV16859
Preliminary Product Preview
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYM B OL
PAR AM ETER S
VDD = 2.5V ±0.2V
M IN M AX
fcl o ck
tPD
tRST
tSL
tSU
Th
Clock frequency
Clock to output time
Reset to output time
Output slew rate
Setup time, fast slew rate 2, 4
Setup time, slow slew rate 3, 4
Hold time, fast slew rate 2, 4
Hold time, slow slew rate 3, 4
Data before CK, CK#
Data after CK, CK#
TBD
1
0 .7 5
0 .9
0 .7 5
0 .9
200
5
4
Note s:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate=1V/ns.
3 - For data signal input slew rate==0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rates are==1V/ns.
UNITS
MHz
ns
ns
V/ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
SYM B OL
Fro m
(In p u t )
To
(Ou t p u t )
VDD = 2.5V ±0.2V
UNITS
M IN
TYP MAX
fmax
200 MHz
tPD CLK, CLK#
Q 1.1
2.8 ns
tph1 CLK, CLK#
Q
5 ns
Third party brands and names are the property of their respective owners.
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