PDF ICSSSTVA16857 Data sheet ( Hoja de datos )

Número de pieza	ICSSSTVA16857
Descripción	DDR 14-Bit Registered Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. DDR 14-Bit Registered Buffer ICSSSTVA16857 Recommended Applications: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers • DDR400 recommended (backward compatible to DDR200/266/333) Product Features: • Exceeds "SSTVN16857" performance • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation - VDD = 2.3V to 2.7V • 48 pin TSSOP package Truth Table1 RESET# L H H H Inputs CLK CLK# X or X or Floating Floating ↑↓ ↑↓ L or H L or H D X or Floating H L X Q Outputs Q L H L Q0(2) Notes: 1. H = High Signal Level L = Low Signal Level ↑ = Transition LOW-to-HIGH ↓ = Transition HIGH -to LOW X = Irrelevant 2. Output level before the indicated steady state input conditions were established. Block Diagram CLK CLK# RESET# 38 39 34 D1 VREF 48 35 Pin Configuration Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK# CLK VDD GND VREF RESET# D8 D9 D10 D11 D12 VDD GND D13 D14 48-Pin TSSOP 6.10 mm. Body, 0.50 mm. pitch = TSSOP R CLK D1 1 Q1 0932A—05/12/04 To 13 Other Channels 1 page ICSSSTVA16857 DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700) TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL PARAMETERS CONDITIONS VDDQ MIN TYP VIK II = -18mA 2.3V VOH IOH = -100µA 2.3V-2.7V VDDQ - 0.2 IOH = -8mA 2.3V 1.95 VOL IOL = 100µA IOL = 8mA 2.3V-2.7V 2.3V II All Inputs Standby (Static) VI = VDD or GND RESET# = GND 2.7V IDD Operating (Static) VI = VIH(AC) or VIL(AC), RESET# = VDD 25 Dynamic operating (clock only) RESET# = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK# switching 30 50% duty cycle. RESET# = VDD, IO = 0 IDDD VI = VIH(AC) or VIL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half 2.7V 10 clock frequency, 50% duty cycle rOH Output High IOH = -16mA 2.3V-2.7V 7 13.5 rOL Output Low IOL = 16mA 2.3V-2.7V 7 13 rO(D) [rOH - rOL] each separate bit IO = 20mA, TA = 25° C 2.5V Ci Data Inputs CLK and CLK# VI = VREF ±350mV VICR = 1.25V, VI(PP) = 360mV 2.5V 2.5 2.5 Notes: 1 - Guaranteed by design, not 100% tested in production. MAX -1.2 0.2 0.35 ±5 0.01 20 20 4 3.5 3.5 UNITS V µA µA mA µ/clock MHz µA/ clock MHz/data Ω Ω Ω pF 0932A—05/12/04 5 5 Page

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