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PDF CLC503 Data sheet ( Hoja de datos )

Número de pieza CLC503
Descripción Comlinear CLC503 180MHz / Differential-Output Amplifier
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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N
Comlinear CLC503
180MHz, Differential-Output Amplifier
August 1996
General Description
The Comlinear CLC503 is a single-ended to differential amplifier.
It utilizes a pair of closed-loop transconductance amplifiers to
provide wideband, high fidelity, differential output signals. Internal
resistors set the differential gain to 2V/V. With a ground-centered
2Vpp input signal, the CLC503 will produce a 4Vpp differential
output signal. This differential output signal is centered around an
adjustable common mode voltage. An independent input controls
the common mode output voltage. The CLC503 has harmonic
distortion products of -77dBc or less, and a signal to noise ratio of
72dB. The output stage is optimized for loads with signal ranges
between +0.7 and +3.9 volts, such as those found on single
supply CMOS ADCs. Overdrive recovery time of the CLC503
and following circuitry is optimized by the output limiting of the
CLC503. The power down pin (PDN) allows for power savings
in applications where unused circuitry is placed in a low
power mode.
Features
s -77dBc distortion (10MHz, 4Vpp)
s 72dB SNR (4Vpp)
s 15ns settling (0.1%)
s 180MHz bandwidth
Applications
s Single-to-differential conversion
s Single supply ADC signal conditioner
Harmonic Distortion vs. Amplitude
-60
RL = 2k
-65
-70
10MHz
5MHz
-75
The CLC503 is an ideal amplifier to drive the differential inputs
of the Comlinear CLC949, 12-bit, 20MSPS, analog-to-digital
converter. It is tailored for driving single supply, differential
input, analog-to-digital converters which require fast settling, high
fidelity inputs.
-80
-85
-90
0
2MHz
1MHz
1234
Output Amplitude (Vpp)
5
Typical Application Diagram
ADC Clock
Power Down
74AC04
Vin
0.1µF
6.8µF
CLC503
PDN
Vin
GND
VEE
Vcm
+Vo
-Vo
VCC
-5V
0.1µF
VREFMO BIASC
CLK
0.1µF
6.8µF
+5V
VINP
VINN
CLC949
12b/20MSPS ADC
VCC GND
0.1µF
PDN
Vin
GND
VEE
Pinout
SOIC
2K
AMP
2K CORE
Vcm
+Vo
-Vo
VCC
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com

1 page




CLC503 pdf
s Pin 1
Power Down (PDN): The power down pin takes
CMOS input levels. Use this to decrease the
power from 250mW to 40mW. This is not a
signal disable pin. A CMOS gate will drive this
input. The quiescent supply current will be
decreased when PDN is at least 1V higher than
Vcm. When the current is turned off, the output
voltage Vo, will go to approximately 4.3V. An
internal pull down resistor of 10k allows PDN to
be left open when not used.
s Pin 2
Input Voltage (Vin): This is the signal input. The
recommended input range is ±1V. The linear
operating range is approximately ±1.4V This
input controls the differential output voltage.
Because of the closed loop nature of the trans-
conductance stage, the transfer function is highly
linear. Refer to Output Voltage pin for output
signal limitations.
s Pin 3
Ground (GND): Tie to low impedance analog
ground.
s Pins 4 and 5
Power Supplies (VEE and VCC): For optimum
performance, use linear ±5V power supplies.
Use bypass capacitors of 0.1µF and 6.8µF on the
power supply lines to decrease any noise that
could be injected into the circuit by the power
supplies. Place the bypass capacitors as close
to the device pins as possible. Remove the
ground plane from the board underneath the
device to eliminate parasitic capacitance. Refer
to Printed Circuit Board Layout section for
more layout suggestions.
s Pins 6 and 7
Output Voltage (-Vo and +Vo): These are the
differential signal output pins. The output voltage
at these pins is limited to 0.7V to 3.9V. The
output recovery time after exceeding these limits
is approximately 40ns. The output voltage can
be defined as:
+Vo = Vcm + Vin
-Vo = Vcm Vin
Vodiff = +Vo (-Vo ) = 2Vin
Vocm
=
+Vo
(-Vo )
2
=
Vcm
s Pin 8
Common-Mode Voltage (Vcm): This input sets
the common-mode output operating points. The
common mode input voltage can range from 1.5V
to 3.5V. Refer to Output Voltage pin discussion
for limitations on the output range.
Design Information
Load: The CLC503 is intended to drive high speed
CMOS analog-to-digital converters, such as the
CLC949. Resistive loading will affect the gain and
common mode offset. It is not recommended to drive
resistive loads below 10kwith this part. See Figure 5
for gain vs. load with specified range in device output
resistance.
2.5
Ro = 600= Romax
2
1.5
Ro = 400= Romin
1
0.5
0
100
1000
10000
100000
Load Resistance ()
03 Fi
Figure 5: Gain vs. Resistive Load
Settling Time: The CLC503 settles to 0.1% in 15ns
with a 5pF load, the input capacitance of the CLC949.
Refer to the Settling Time vs. Capacitive Load plot in
the Typical Performance Characteristics section.
Power Dissipation
To calculate the power dissipation, PT, for the CLC503,
use the following equation:
( )PT = ICC VCC VEE
Printed Circuit Board Layout
The performance of the CLC503 is strongly dependent
on proper layout, and adequate power supply
decoupling. The parasitic capacitance at the output of
the CLC503 and the input to the CLC949, or any other
analog-to-digital converter, must be kept to a minimum.
Consider the following guidelines:
s Use a ground plane.
s Bypass power supply pins with monolithic
capacitors of 0.1µF and with 6.8µF tantalum
capacitors. Place the capacitors less than 0.1"
(3mm) from the pin.
s Remove the ground plane underneath the
device and 0.1" (3mm) from all input/output
pads.
Interfacing the CLC503 with the CLC949
The CLC503 can be easily interfaced with the CLC949
as shown in Figure 6. An evaluation board is available
for proto-typing and measurements.
5 http://www.national.com

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