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PDF M30L0R7000xx Data sheet ( Hoja de datos )

Número de pieza M30L0R7000xx
Descripción 128 Mbit (8Mb x16 / Multiple Bank / Multi-Level / Burst) / 1.8V Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M30L0R7000T0
M30L0R7000B0
128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)
1.8V Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
– VDD = 1.7V to 2.0V for program, erase and
read
– VDDQ = 1.7V to 2.0V for I/O Buffers
– VPP = 9V for fast program (12V tolerant)
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Program
MEMORY ORGANIZATION
– Multiple Bank Memory Array: 8 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Package
FBGA
TFBGA88 (ZAQ)
8 x 10mm
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code: 88C4h.
– Bottom Device Code: 88C5h
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
December 2004
1/83

1 page




M30L0R7000xx pdf
M30L0R7000T0, M30L0R7000B0
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19.TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline . . . . 52
Table 26. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data . . . . . . . 52
Figure 20.TFBGA88 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 53
Figure 21.TFBGA88 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . . 54
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 29. Top Boot Block Addresses, M30L0R7000T0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 30. Bottom Boot Block Addresses, M30L0R7000B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 32. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 33. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 34. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 36. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 37. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 38. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 39. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 40. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 23.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 24.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 71
Figure 25.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 26.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 28.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 75
Figure 29.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . 76
APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 41. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 42. Command Interface States - Modify Table, Next Output State . . . . . . . . . . . . . . . . . . . . 79
Table 43. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 44. Command Interface States - Lock Table, Next Output State. . . . . . . . . . . . . . . . . . . . . . 81
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 45. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5/83

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M30L0R7000xx arduino
M30L0R7000T0, M30L0R7000B0
should be as close as possible to the pack-
age). See Figure 9., AC Measurement Load Cir-
cuit. The PCB trace widths should be sufficient
to carry the required VPP program and erase
currents.
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See Table 3., Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures 10, 11, 12 and 13 Read AC Wave-
forms, and Tables 21 and 22 Read AC Character-
istics, for details of when the output becomes
valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 16 and 17, Write AC Waveforms, and
Tables 23 and 24, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at VIL during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high imped-
ance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in standby when
Chip Enable and Reset are at VIH. The power con-
sumption is reduced to the standby level IDD4 and
the outputs are set to high impedance, indepen-
dently from the Output Enable or Write Enable in-
puts. If Chip Enable switches to VIH during a
program or erase operation, the device enters
Standby mode when finished.
Reset. During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL.
The power consumption is reduced to the Standby
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
VSS during a Program or Erase, this operation is
aborted and the memory content is no longer valid.
Table 3. Bus Operations
Operation
E G W L RP
Bus Read
Bus Write
VIL VIL VIH VIL(2) VIH
VIL VIH VIL VIL(2) VIH
Address Latch
VIL X VIH VIL VIH
Output Disable
VIL VIH VIH X VIH
Standby
VIH X X X VIH
Reset
X X X X VIL
Note: 1. X = Don't care.
2. L can be tied to VIH if the valid address has been previously latched.
3. Depends on G.
4. WAIT signal polarity is configured using the Set Configuration Register command.
WAIT(4)
DQ15-DQ0
Data Output
Data Input
Data Output or Hi-Z (3)
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
11/83

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