PDF W256 Data sheet ( Hoja de datos )

Número de pieza	W256
Descripción	12 Output Buffer for 2 DDR and 3 SRAM DIMMS
Fabricantes	Cypress Semiconductor
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No Preview Available ! W256 12 Output Buffer for 2 DDR and 3 SRAM DIMMS Features • One input to 12 output buffer/drivers • Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS • One additional output for feedback • SMBus interface for individual output control • Low skew outputs (< 100 ps) • Supports 266 MHz and 333 MHz DDR SDRAM • Dedicated pin for power management support • Space-saving 28-pin SSOP package Functional Description The W256 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 12 outputs. Designers can configure these outputs to support 3 unbuffered standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can be used in conjunction with the W250-02 or similar clock synthesizer for the VIA Pro 266 chipset. The W256 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull-up). Block Diagram BUF_IN VDD3.5_2.5 SDATA SCLOCK PWR_DWN# SMBus Decoding & Powerdown Control SEL_DDR FBOUT DDR0T_SDRAM0 DDR0C_SDRAM1 DDR1T_SDRAM2 DDR1C_SDRAM3 DDR2T_SDRAM4 DDR2C_SDRAM5 DDR3T_SDRAM6 DDR3C_SDRAM7 Pin Configuration[1] FBOUT PWR_DWN# DDR0T_SDRAM0 DDR0C_SDRAM1 VDD3.3_2.5 GND DDR1T_SDRAM2 DDR1C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR2T_SDRAM4 DDR2C_SDRAM5 VDD3.3_2.5 SSOP Top View 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 SEL_DDR DDR5T_SDRAM10 DDR5C_SDRAM11 VDD3.3_2.5 GND DDR4T_SDRAM8 DDR4C_SDRAM9 VDD3.3_2.5 GND DDR3T_SDRAM6 DDR3C_SDRAM7 GND SCLK SDATA DDR4T_SDRAM8 DDR4C_SDRAM9 DDR5T_SDRAM10 DDR5C_SDRAM11 Note: 1. Internal 100K pull-up resistors present on inputs marked with . Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07256 Rev. C Revised August 30, 2004 1 page Switching Characteristics[4] Parameter Name Test Conditions – Operating Frequency – Duty Cycle[4,5] = t2 ÷ t1 Measured at 1.4V for 3.3V outputs Measured at VDD/2 for 2.5V outputs. t3 SDRAM Rising Edge Rate[4] Measured between 0.4V and 2.4V t4 SDRAM Falling Edge Rate[4] Measured between 2.4V and 0.4V t3d DDR Rising Edge Rate[4] Measured between 20% to 80% of output (Refer to Figure 1) t4d DDR Falling Edge Rate[4] Measured between 20% to 80% of output (Refer to Figure 1) t5 Output to Output Skew[4] All outputs equally loaded t6 Output t4o Output Skew for SDRAM[2] All outputs equally loaded t7 SDRAM Buffer HH Prop. Delay[4] Input edge greater than 1 V/ns t8 SDRAM Buffer LLProp. Delay[4] Input edge greater than 1 V/ns Switching Waveforms Duty Cycle Timing t1 t2 Min. 66 INDC –5% 1.0 1.0 0.5 0.5 5 5 W256 Typ. Max. 180 INDC +5% Unit MHz % 2.50 2.50 1.50 V/ns V/ns V/ns 1.50 V/ns 100 ps 150 ps 10 ns 10 ns All Outputs Rise/Fall Time 2.4V OUTPUT 0.4V t3 Output-Output Skew OUTPUT 2.4V 0.4V t4 3.3V 0V OUTPUT t5 Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns. Document #: 38-07256 Rev. *C Page 5 of 9 5 Page

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