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PDF TC5299J Data sheet ( Hoja de datos )
| Número de pieza | TC5299J | |
| Descripción | FAST ETHERNET PCMCIA LAN CONTROLLER | |
| Fabricantes | ETC | |
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TC5299J
TC5299J
FAST ETHERNET PCMCIA
LAN CONTROLLER
4FL No. 106 Hsin-Tai Wu Road,
Sec. 1, Hsichih,
Taipei Hsien, Taiwan R.O.C.
TEL: 886-2-2696-1669
FAX: 886-2-2696-2220
http:\\www.tmi.com.tw
-1- Ver. 0.1
07/04/01
1 page  
TC5299J
3.2 Signal Description
PCMCIA Bus Interface Pins
Symbol
Pin #
SA[9:0]
SD[15:8]
SD[7:0]
RST
3-5
7-12,
14
114-117,
119-120,
122-123,
31-29,
27-26,
24-22
16
RSTZ
WAIT*
REG*
105
17
19
IOR*
IOW*
OE*
WE*
INPACK*
IO16*
INT*
(RDY/BSY*)
126
2
127
34
18
21
125
CE1*
35
I/O Description
I The address signal lines of PCMCIA Bus are used to select a
register to be read or written and attribute memory enabled.
I/O Register Access, with DMA inactive, SD0-SD7 are used to
read/write register data. SD8-SD15 invalid during this state.
Remote DMA Bus Cycle, SD0-SD15 contain packet data.
Direction of transfer depends on Remote read/write.
I/O RST is active high and places the TC5299J in a reset mode
immediately. During falling edge the TC5299J controller loads
the configuration from JMP0 – JMP8.
O RSTZ is an active low signal. It is an inverted signal of RST.
O This pin is set low to insert wait states during Remote DMA
transfer.
I REG is an active low input used to determine whether a host
access is to Attribute memory or to common memory. If REG is
low the access is to attribute memory, if REG* is high the access
is to common memory. REG* is also asserted low for all accesses
to the TC5299J IO Registers.
I Read Strobe: Strobe from host to read registers or Remote DMA
read.
I Write Strobe: Strobe from host to read registers or Remote DMA
write.
I Host memory read strobe, when OE* and REG* both low the
attribute memory can be read. When OE* is low and REG* is
high common memory can be read.
I Host memory write strobe, After Power reset if TC5299J is
configured to memory write enable, then WE and REG* is both
low, Attribute memory can be written. When WE is low and
REG* is high common memory can be written.
O An active low signal. Asserted if the host access register or
Remote DMA read cycle.
O IO16* is driven by TC5299J to support host 16 bits access cycle.
O While the TC5299J is configured as a memory device, this pin
servers as RDY/BSY* pin, If the TC5299J is ready to perform a
transfer, this pin is set high. When TC5299J is operated at I/O
mode, this pin is used as an interrupt pin. It indicates that the
TC5299J needs host service. RDY/BSY* state can be read from
the pin Replacement Register (CCR2). While LAN and MODEM
both functions are enabled and IntSel bit in control Register
(CCR5) is zero. This pin output is logical OR of LAN and
MODEM interrupt.
I Card enable 1, is active low signals driven by the host. This
signal provides a card select based on the address decode (decode
by the host).
-5- Ver. 0.1
07/04/01
5 Page 
TC5299J
TC5299J Controller actually has 32k-address range but only does partial decoding on these devices. 0000H – 001FH is
PROM address and 4000H – 7FFFH is Buffer RAM address, otherwise is reserved. To access either the PROM or the
RAM buffer which user must initiate a Remote DMA transfer between the I/O port and memory.
Remote Read/Write Cache:
The TC5299J Controller includes 4 words cache internally. On a remote read the TC5299J Controller moves data from
memory buffer to the cache buffer; the TC5299J moves data continuously until the cache buffer is full. On a remote
write the system can writes data into the cache buffer until the 4 words cache buffer is full.
4.3 Attribute Memory Mapping
PCMCIA CIS Structures & Decode Function:
The TC5299J supports access to 1K of attribute Memory. Attribute memory is defined by the PCMCIA standard to be
comprised of the card information structure and four 8-bits Card Configuration Registers. These four registers are
contained in the TC5299J.
4.3.1 Attribute Memory Map
The attribute Memory map for a PCMCIA card is shown below.
Address
00H-3E0H
3F0H (CCR4)
3F2H (CCR5)
3F4H-3F6H
3F8H(CCR0)
3FAH(CCR1)
3FCH(CCR2)
3FEH(CCR3)
Description
Attribute Memory
I/O Event indication Register
Control Register
Reserved
Configuration Option Register
Card Configuration and Status Register
Pin Replacement Register
Reserved
Card Option Registers 0 (R/W): 3F8H (CCR0)
D7 D6 D5 D4 D3 D2 D1 D0
SRESET XX PCMIOEN XX XX XX PJ1 PJ0
Name
PJ0-PJ1
PCMIOEN
SRESET
XX
Description
If JMP1 pulled low during power on reset and FUNC=0, The two bits select one of
4 I/O base address. (shows as below)
To set high make the card enter I/O mode. The function also can be set by JMP0
(MCS) when Power On Reset.
Setting this bit to high, place the card enter reset mode.
Reserved
JMP1 does not pull-low during power on reset.
-11- Ver. 0.1
07/04/01
11 Page | ||
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