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PDF MAX1437 Data sheet ( Hoja de datos )
| Número de pieza | MAX1437 | |
| Descripción | Octal / 12-Bit / 50Msps / 1.8V ADC with Serial LVDS Outputs | |
| Fabricantes | Maxim Integrated Products | |
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19-3645; Rev 0; 4/05
EVAALVUAAILTAIOBNLEKIT
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
General Description
The MAX1437 octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1437 operates from a 1.8V single
supply and consumes only 768mW (96mW per chan-
nel) while delivering a 69.9dB (typ) signal-to-noise ratio
(SNR) at a 5.3MHz input frequency. In addition to low
operating power, the MAX1437 features a power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc-
ture allows the use of an external reference for applica-
tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip PLL
generates the high-speed serial low-voltage differential
signal (LVDS) clock.
The MAX1437 has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s complement or binary format.
The MAX1437 offers a maximum sample rate of 50Msps.
See the Pin-Compatible Versions table below for higher-
and lower-speed versions. This device is available in a
small, 14mm x 14mm x 1mm, 100-pin TQFP package
with exposed paddle and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
Features
♦ Excellent Dynamic Performance
69.9dB SNR at 5.3MHz
96dBc SFDR at 5.3MHz
95dB Channel Isolation
♦ Ultra-Low Power
96mW per Channel (Normal Operation)
♦ Serial LVDS Outputs
♦ Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
♦ LVDS Outputs Support Up to 30 Inches FR-4
Backplane Connections
♦ Test Mode for Digital Signal Integrity
♦ Fully Differential Analog Inputs
♦ Wide Differential Input Voltage Range (1.4VP-P)
♦ On-Chip 1.24V Precision Bandgap Reference
♦ Clock Duty-Cycle Equalizer
♦ Compact, 100-Pin TQFP Package with Exposed
Paddle
♦ Evaluation Kit Available (Order MAX1437EVKIT)
Ordering Information
PART
TEMP RANGE
MAX1437ECQ -40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
100 TQFP-EP*
(14mm x 14mm x 1mm)
Pin-Compatible Versions
PART
MAX1434
SAMPLING RATE
(Msps)
50
RESOLUTION
(BITS)
10
MAX1436
MAX1438**
40
65
12
12
**Future product—contact factory for availability.
Pin Configuration appears at the end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF,
CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (Note 6)
CONDITIONS
Data Valid to CLKOUT Rise/Fall
tOD Figure 5 (Note 7)
MIN TYP MAX UNITS
(tSAMPLE /
24)
- 0.15
(tSAMPLE /
24)
+ 0.15
ns
CLKOUT Output-Width High
tCH Figure 5
tSAMPLE /
12
ns
CLKOUT Output-Width Low
FRAME Rise to CLKOUT Rise
tCL Figure 5
tCF Figure 4 (Note 7)
Sample CLK Rise to FRAME Rise
Crosstalk
Gain Matching
Phase Matching
tSF Figure 4 (Note 7)
CGM
CPM
(Note 2)
fIN = 5.3MHz (Note 2)
fIN = 5.3MHz (Note 2)
tSAMPLE /
12
(tSAMPLE /
24)
- 0.15
(tSAMPLE /
24)
+ 0.15
(tSAMPLE /
2)
+ 1.1
(tSAMPLE /
2)
+ 2.6
-95
±0.1
±0.25
ns
ns
ns
dB
dB
Degrees
Note 1: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 2: See definition in the Parameter Definition section at the end of this data sheet.
Note 3: See the Common-Mode Output (CMOUT) section.
Note 4: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal
bandgap reference and enable external reference mode.
Note 5: Measured using CREFP to GND = 1µF and CREFN to GND = 1µF. tENABLE time may be lowered by using smaller capacitor values.
Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz
(50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
FFT PLOT
(16,384-POINT DATA RECORD)
fCLK = 50.1523789MHz
fIN = 5.304814MHz
AIN = -0.5dBFS
SNR = 69.959dB
SINAD = 69.950dB
THD = -96.635dBc
SFDR = 96.503dBc
HD2 HD3
5 10 15 20
FREQUENCY (MHz)
25
FFT PLOT
(16,384-POINT DATA RECORD)
0
-10
fCLK = 50.1523789MHz
fIN = 24.0997118MHz
-20 AIN = -0.5dBFS
-30 SNR = 69.707dB
SINAD = 69.672dB
-40 THD = -90.672dBc
-50 SFDR = 93.694dBc
-60
-70
HD2
-80
HD3
-90
-100
-110
0
5 10 15 20
FREQUENCY (MHz)
25
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(16,384-POINT DATA RECORD)
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
fIN(IN1) = 5.304814MHz
fIN(IN2) = 24.0997118MHz
CROSSTALK = 103dB
fIN(IN2)
5 10 15 20
FREQUENCY (MHz)
25
_______________________________________________________________________________________ 5
5 Page 
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
Pin Description (continued)
PIN NAME
FUNCTION
58
FRAMEN
Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME
output aligns to a valid D0 in the output data stream.
59
FRAMEP
Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output
aligns to a valid D0 in the output data stream.
61 CLKOUTN Negative LVDS/SLVS Serial Clock Output
62 CLKOUTP Positive LVDS/SLVS Serial Clock Output
65 OUT3N Channel 3 Negative LVDS/SLVS Output
66 OUT3P Channel 3 Positive LVDS/SLVS Output
68 OUT2N Channel 2 Negative LVDS/SLVS Output
69 OUT2P Channel 2 Positive LVDS/SLVS Output
72 OUT1N Channel 1 Negative LVDS/SLVS Output
73 OUT1P Channel 1 Positive LVDS/SLVS Output
78 OUT0N Channel 0 Negative LVDS/SLVS Output
79 OUT0P Channel 0 Positive LVDS/SLVS Output
LVDS Test Pattern Enable. Drive LVDSTEST high to enable the output test pattern (0000 1011
80 LVDSTEST 1101 MSB→ LSB). As with the analog conversion results, the test pattern data is output LSB
first. Drive LVDSTEST low for normal operation.
81
PD
Power-Down Input. Drive PD high to power down all channels and reference. Drive PD low for
normal operation.
82 PLL3 PLL Control Input 3. See Table 1 for details.
83 PLL2 PLL Control Input 2. See Table 1 for details.
84 PLL1 PLL Control Input 1. See Table 1 for details.
85
T/B
Output Format-Select Input. Drive T/B high to select binary output format. Drive T/B low to
select two’s-complement output format.
Negative Reference Bypass Output. Connect a ≥1µF (10µF typ) capacitor between REFP and
90 REFN REFN, and connect a ≥1µF (10µF typ) capacitor between REFN and GND. Place the capacitors
as close to the device as possible on the same side of the printed circuit (PC) board.
Positive Reference Bypass Output. Connect a ≥1µF (10µF typ) capacitor between REFP and
91 REFP REFN, and connect a ≥1µF (10µF typ) capacitor between REFP and GND. Place the
capacitors as close to the device as possible on the same side of the PC board.
Reference Input/Output. For internal reference operation (REFADJ = GND), the reference
93 REFIO output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable
reference voltage at REFIO. Bypass to GND with ≥0.1µF.
Internal/External Reference-Mode-Select and Reference Adjust Input. For internal reference
94
REFADJ
mode, connect REFADJ directly to GND. For external reference mode, connect REFADJ
directly to AVDD. For reference-adjust mode, see the Full-Scale Range Adjustments Using the
Internal Reference section.
95
CMOUT
Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage
for DC-coupled applications. Bypass CMOUT to GND with ≥0.1µF capacitor.
97 IN0P Channel 0 Positive Analog Input
98 IN0N Channel 0 Negative Analog Input
— EP Exposed Paddle. EP is internally connected to GND. Connect EP to GND.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MAX1437.PDF ] | |
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