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PDF IC61LV12816 Data sheet ( Hoja de datos )
| Número de pieza | IC61LV12816 | |
| Descripción | 128K x 16 Hight Speed SRAM with 3.3V | |
| Fabricantes | ICSI | |
| Logotipo |  |
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IC61LV12816
Document Title
128K x 16 Hight Speed SRAM with 3.3V
Revision History
Revision No
History
0A Initial Draft
0B Revise typo on page 6
Draft Date
Remark
September 12,2001
April 23,2004
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
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1 page  
IC61LV12816
TRUTH TABLE
Mode
WE CE OE LB UB
Not Selected
XHXXX
Output Disabled
H
L
H
X
X
X L XHH
Read
HL L LH
HL LHL
HL L L L
Write
L LXLH
L LXHL
LLXLL
I/O PIN
I/O0-I/O7 I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
ISB1, ISB2
ICC
ICC
ICC
1
2
3
4
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
TestConditions
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max. Unit
ICC
Vcc Dynamic Operating
VCC = Max., CE = VIL Com. — 220
— 200
— 180
— 165 mA
Supply Current
IOUT = 0 mA, f = fMAX Ind. — 230
— 210
— 190
— 175
ISB1 TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com. — 30
Ind. — 40
— 30
— 40
— 30
— 40
— 30 mA
— 40
ISB2 CMOS Standby
VCC = Max.,
Com. — 10
— 10
— 10
— 10 mA
Current (CMOS Inputs)
CE ≥ VCC – 0.2V,
Ind. — 15
— 15
— 15
— 15
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
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Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
5
5 Page 
IC61LV12816
WRITE CYCLE NO. 4 (1,3)(LB, UB Controlled, Back-to-Back Write)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
1
OE
CE LOW
t SA
WE
UB, LB
DOUT
DIN
t PWB
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PWB
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
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Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IC61LV12816.PDF ] | |
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