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PDF 82845Mx Data sheet ( Hoja de datos )

Número de pieza 82845Mx
Descripción Chipset Memory Controller Hub Mobile
Fabricantes Intel 
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R
Intel® 845 Family Chipset-Mobile:
82845MP/82845MZ Chipset Memory
Controller Hub Mobile (MCH-M)
Datasheet
April 2002
Order Number: 250687-002

1 page




82845Mx pdf
R Intel® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8.17.
3.8.18.
3.8.19.
3.8.20.
3.8.21.
3.8.22.
3.8.23.
3.8.24.
MBASE1 – Memory Base Address Register – Device #1 ........................... 96
MLIMIT1 – Memory Limit Address Register – Device #1............................ 97
PMBASE1 – Prefetchable Memory Base Address Register – Device #1 ... 98
PMLIMIT1 – Prefetchable Memory Limit Address Register – Device #1 .... 99
BCTRL1 – PCI-PCI Bridge Control Register – Device #1 ......................... 100
ERRCMD1 – Error Command Register – Device #1 ................................ 101
DWTMC – DRAM Write Thermal Management Control ........................... 102
DRTMC – DRAM Read Thermal Management Control ............................ 104
4. System Address Map ............................................................................................................... 105
4.1. Memory Address Ranges ............................................................................................ 105
4.1.1.
4.1.2.
4.1.3.
4.1.4.
4.1.5.
4.1.6.
VGA and MDA Memory Space.................................................................. 106
PAM Memory Spaces................................................................................ 107
ISA Hole Memory Space ........................................................................... 108
TSEG SMM Memory Space ...................................................................... 108
System Bus Interrupt APIC Memory Space .............................................. 109
High SMM Memory Space ........................................................................ 109
4.1.7.
AGP Aperture Space (Device #0 BAR) ..................................................... 109
4.1.8.
AGP Memory and Prefetchable Memory................................................... 109
4.1.9.
Hub Interface A Subtractive Decode ......................................................... 110
4.2. AGP Memory Address Ranges ................................................................................... 110
4.2.1.
AGP DRAM Graphics Aperture ................................................................. 110
4.3. System Management Mode (SMM) Memory Range ................................................... 111
4.3.1.
SMM Space Definition............................................................................... 111
4.3.2.
SMM Space Restrictions ........................................................................... 112
4.4. I/O Address Space ...................................................................................................... 112
4.5. MCH-M Decode Rules and Cross-Bridge Address Mapping ...................................... 112
4.5.1.
4.5.2.
Decode Rules for the Hub Interface A ...................................................... 112
AGP Interface Decode Rules .................................................................... 113
5. Functional Description.............................................................................................................. 114
5.1. Host Interface Overview .............................................................................................. 114
5.1.1.
Dynamic Bus Inversion.............................................................................. 114
5.1.2.
System Bus Interrupt Delivery................................................................... 114
5.1.3.
Upstream Interrupt Messages................................................................... 115
5.2. System Memory Interface ........................................................................................... 115
5.2.1.
DDR Interface Overview............................................................................ 115
5.2.2.
Memory Organization and Configuration................................................... 116
5.2.2.1. Configuration Mechanism for SO-DIMMs..................................... 116
5.2.2.1.1. Memory Detection and Initialization............................ 116
5.2.2.1.2. SMBus Configuration and Access of the Serial
Presence Detect Ports................................................ 116
5.2.2.1.3. Memory Register Programming ................................. 116
5.2.3.
DRAM Performance Description ............................................................... 117
5.2.3.1. Data Integrity (ECC) ..................................................................... 117
5.3. AGP Interface Overview.............................................................................................. 117
5.3.1.
AGP Target Operations............................................................................. 118
5.3.2.
AGP Transaction Ordering........................................................................ 119
5.3.3.
AGP Signal Levels .................................................................................... 119
5.3.4.
4x AGP Protocol........................................................................................ 119
5.3.5.
Fast Writes ................................................................................................ 119
5.3.6.
AGP FRAME# Transactions on AGP........................................................ 120
250687-002
Datasheet
5

5 Page





82845Mx arduino
R Intel® 82845MP/82845MZ Chipset-Mobile (MCH-M)
Terminology
MCH-M - The Mobile Memory Controller Hub-M component that contains the processor interface,
DRAM controller, and AGP interface. It communicates with the I/O controller hub (ICH3-M) and other
IO controller hubs over proprietary interconnect called the hub interface.
ICH3-M - The Mobile I/O Controller Hub 3-M component that contains the primary PCI interface, LPC
interface, USB, ATA-100, AC’97, and other IO functions. It communicates with the Intel®
845MP/845MZ Chipset MCH-M over a proprietary interconnect called hub interface.
Host - This term is used synonymously with processor.
Core - The internal base logic in the MCH-M.
System Bus - Processor-to-MCH-M interface. The Enhanced Mode of the Scalable Bus is the P6 Bus
plus enhancements, consisting of source synchronous transfers for address and data, and system bus
interrupt delivery. The Mobile Intel Pentium 4 Processor-M implements a subset of Enhanced Mode.
Hub interface - The proprietary hub interconnect that ties the MCH-M to the ICH3-M. In this document
hub interface cycles originating from or destined for the primary PCI interface on the ICH3-M is
generally referred to as hub interface cycles.
Accelerated Graphics Port (AGP) - Refers to the AGP interface that is in the MCH-M. It supports
AGP 2.0 compliant components only with 1.5V signaling level. PIPE# and SBA addressing cycles and
their associated data phases are generally referred to as AGP transactions. FRAME# cycles over the AGP
bus are generally referred to as AGP/PCI transactions.
PCI_A - The physical PCI bus, driven directly by the ICH3-M component. It supports 5-V, 32-bit, 33-
MHz PCI 2.2 compliant components. Communication between PCI_A and MCH-M occurs over hub
interface. Note: Even though it is referred to as PCI_A it is not PCI Bus #0 from a configuration
standpoint.
Full Reset - A Full MCH-M Reset is defined in this document when RSTIN# is asserted.
System Bus - Synonymous with Host or Front Side Bus
GART - Graphics Aperture Re-map Table. This table contains the page re-map information used during
AGP aperture address translations.
GTLB - Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.
UP – Uniprocessor
DBI – Dynamic Bus inversion
MSI – Message Signaled Interrupts. MSI’s allow a device to request interrupt service via a standard
Memory Write transaction instead of through a hardware signal.
IPI – Inter Processor Interrupt
Word – 16 bits = 2 bytes
Dword (DW) – Doubleword: 32bits = 4 bytes
250687-002
Datasheet
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