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PDF DS1558 Data sheet ( Hoja de datos )

Número de pieza DS1558
Descripción Watchdog Clock with NV RAM Control
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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No Preview Available ! DS1558 Hoja de datos, Descripción, Manual

DS1558
Watchdog Clock with NV RAM Control
www.maxim-ic.com
FEATURES
§ Integrated real-time clock (RTC), power-fail
control circuit, and NV RAM controller
§ Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations
§ Century register
§ Greater than 10 years of timekeeping and data
retention in the absence of power with small
lithium coin cell(s) and low-leakage SRAM
§ Precision power-on reset
§ Programmable watchdog timer and RTC
alarm
§ BCD-coded year, month, date, day, hours,
minutes, and seconds with automatic leap-
year compensation valid up to the year 2100
§ Battery voltage-level indicator flag
§ Power-fail write protection allows for ±10%
VCC power-supply tolerance
§ Underwriters Laboratory (UL) recognized
ORDERING INFORMATION
PART
DS1558Y
DS1558W
PIN-
PACKAGE
48 TQFP
48 TQFP
VCC (V)
5
3.3
TOP
MARK
DS1558B
DS1558D
PIN CONFIGURATION
TOP VIEW
N.C.
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
DS1558
36
35
34
33
32
31
30
29
28
27
26
25
A15
VBAT1
WE
IRQ/FT
A13
A8
A9
A11
OE
A10
CE
OER
TQFP
Package Dimension Information:
www.maxim-ic.com/DallasPackInfo
PIN DESCRIPTION
A0–A18
- Address Input
DQ0–DQ7
- Data Input/Outputs
IRQ /FT
- Interrupt, Frequency-Test
Output (Open Drain)
RST - Power-On Reset Output
(Open Drain)
CE - Chip-Enable Input
CER - Chip-Enable RAM
OE - Output-Enable Input
OER - Output-Enable RAM
WE
VCC
VCCO
GND
N.C.
X1, X2
VBAT1
VBAT2
- Write Enable
- Power-Supply Input
- VCC Out to RAM
- Ground
- No Connection
- Crystal Connection
- +3V Battery Input
- +3V Battery Input
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata..
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REV: 082503

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DS1558 pdf
Table 1. OPERATING MODES
VCC
VCC > VPF
CE OE WE DQ0–DQ7
VIH X X
VIL X VIL
VIL VIL VIH
VIL VIH VIH
High-Z
DIN
DOUT
High-Z
VSO < VCC < VPF X
XX
High-Z
VCC < VSO < VPF X
XX
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
DS1558
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows
ripple-through access to any valid address location. Valid data is available at the DQ pins within tAA after
the last address input is stable, provided that CE and OE access times are satisfied. If CE or OE access
times are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable
access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time
(tOH), but then goes indeterminate until the next address access.
DATA WRITE MODE
The DS1558 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent
read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH
afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE then disables the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is
switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater
than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
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DS1558 arduino
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground
Storage Temperature Range
Soldering Temperature Range
DS1558
-0.3V to +6.0V
-55°C to +125°C
See IPC/JEDEC J-STD-020A
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 3.3V ±10% or 5V ±10%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
Logic 1 Voltage (All Inputs)
MIN
TYP
MAX UNITS NOTES
VCC = +5V ±10%
VCC = +3.3V ±10%
Logic 0 Voltage (All Inputs)
VIH
VIH
2.2
2.0
VCC + 0.3V
VCC + 0.3V
V
V
1
1
VCC = +5V ±10%
VCC = +3.3V ±10%
Battery Voltage
VIL
VIL
VBAT
-0.3 +0.8
-0.3 +0.6
2.5 3.3 3.7
V
1
1
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