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PDF UBA1707 Data sheet ( Hoja de datos )

Número de pieza UBA1707
Descripción Cordless telephone / answering machine line interface
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
UBA1707
Cordless telephone, answering
machine line interface
Product specification
Supersedes data of 1998 Jun 11
File under Integrated Circuits, IC03
1999 Feb 17

1 page




UBA1707 pdf
Philips Semiconductors
Cordless telephone, answering machine
line interface
Product specification
UBA1707
PINNING
SYMBOL PIN
DESCRIPTION
SLPE
1 connection for slope resistor
LN 2 positive line terminal
REG
3 line voltage regulator decoupling
LVI 4 negative line voltage sense input
RGL
5 reference for current regulation mode
LCC
6 line current control output
CST
7 input for stability capacitor
RXO
8 receive amplifier output
AGC
9 automatic gain control/line loss
compensation adjustment
RXI 10 receiver amplifier input
EHI 11 electronic hook switch control input
DATA
12 serial bus data input
EN 13 programming serial bus enable input
CLK 14 serial bus clock input
AXI 15 auxiliary amplifier input
AXO
TXI
TXI+
16 auxiliary amplifier output
17 inverted transmit amplifier input
18 non-inverted transmit amplifier input
SWI3
19 NPN open-collector output 3
SWI2
20 NPN open-collector output 2
SWI1
21 NPN open-collector output 1
GND
22 ground reference
LSPGND 23 ground reference for the loudspeaker
amplifier
LSAO
24 loudspeaker amplifier output
VCC
LSAI1
25 supply voltage
26 loudspeaker amplifier input 1
LSAI2
27 loudspeaker amplifier input 2
DLC
28 dynamic limiter timing adjustment
handbook, halfpage
SLPE 1
28 DLC
LN 2
27 LSAI2
REG 3
26 LSAI1
LVI 4
RGL 5
25 VCC
24 LSAO
LCC 6
23 LSPGND
CST 7
RXO 8
22 GND
UBA1707
21 SWI1
AGC 9
20 SWI2
RXI 10
19 SWI3
EHI 11
18 TXI+
DATA 12
17 TXI
EN 13
16 AXO
CLK 14
15 AXI
MGK704
Fig.2 Pin configuration.
1999 Feb 17
5

5 Page





UBA1707 arduino
Philips Semiconductors
Cordless telephone, answering machine
line interface
Product specification
UBA1707
The EHI input can also be used for pulse dialling or
register recall (timed loop break). During line breaks
(voltage at pin EHI is LOW or open-circuit), the voltage
regulator is switched off and the capacitor at pin REG is
internally disconnected to prevent its discharge. As a
result, the voltage stabilizer will have negligible switch-on
delay after line interruptions. This minimizes the
contribution of the IC to the current waveform during pulse
dialling or register recall.
When the UBA1707 is in power-down mode (bit PD at
logic 1), the TPDARL transistor is forced to be turned off
whatever the voltage applied at pin EHI.
SET IMPEDANCE
In the audio frequency range, the dynamic impedance
between pins LN and GND (illustrated in Fig.8) is mainly
determined by the ZSET impedance.
The impedance introduced by the external TNSW transistor
connected between pin GND and the negative line
terminal (LN) is negligible.
handbook, halfpage LN
LEQ
RP
ZSET
619
Vref
SLPE
GND
RSLPE
10
REG
CREG
4.7 µF
MGL215
TRANSMIT AMPLIFIER (PINS TXI+ AND TXI)
The UBA1707 has symmetrical transmit inputs TXI+ and
TXI. The input impedance between pins TXI+ or TXIand
GND is 21 k. The voltage gain from pins TXI+ or TXIto
pin LN is set at 11.6 dB with 600 line load (Zline) and
619 set impedance. The inputs are biased at
2 × Vd 1.4 V, with Vd representing the diode voltage.
Automatic gain control is provided on this amplifier for line
loss compensation.
RECEIVE AMPLIFIER (PINS RXI AND RXO; BIT RXM)
The receive amplifier (see Fig.9) has one input (RXI) and
one output (RXO). The input impedance between pins
RXI and GND is 21 k. The rail-to-rail output stage is
designed to drive a 500 µA peak current. The output
impedance at pin RXO is approximately 100 .
The voltage gain from pin RXI to pin RXO is set at 37.9 dB.
This gain value compensates typically the attenuation of
the anti-sidetone network (see Fig.10). The output as well
as the input are biased at 2 × Vd 1.4 V. Automatic gain
control is provided on this amplifier for line loss
compensation. This amplifier can be muted by activating
the receive mute function (bit RXM at logic 1).
Leq = CREG × RSLPE × RP
RP = internal resistance = 35 k.
Fig.8 Equivalent impedance between
LN and GND.
1999 Feb 17
11

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